<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26258">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/i82870: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I751b72733de2e3bf3aebd1bc85dc83ec1c406faa<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/i82870/ioapic.c<br>M src/southbridge/intel/i82870/pcibridge.c<br>2 files changed, 3 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/26258/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c</span><br><span>index da7da5e..6c65301 100644</span><br><span>--- a/src/southbridge/intel/i82870/ioapic.c</span><br><span>+++ b/src/southbridge/intel/i82870/ioapic.c</span><br><span>@@ -9,7 +9,7 @@</span><br><span> </span><br><span> static int num_p64h2_ioapics = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void p64h2_ioapic_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void p64h2_ioapic_enable(struct device *dev)</span><br><span> {</span><br><span>         /* We have to enable MEM and Bus Master for IOAPIC */</span><br><span>        uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;</span><br><span>@@ -26,7 +26,7 @@</span><br><span>  * @param dev PCI bus/device/function of P64H2 IOAPIC.</span><br><span>  *            NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void p64h2_ioapic_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void p64h2_ioapic_init(struct device *dev)</span><br><span> {</span><br><span>    uint32_t memoryBase;</span><br><span>         int apic_index, apic_id;</span><br><span>diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c</span><br><span>index e8d890a..01cdd14 100644</span><br><span>--- a/src/southbridge/intel/i82870/pcibridge.c</span><br><span>+++ b/src/southbridge/intel/i82870/pcibridge.c</span><br><span>@@ -6,7 +6,7 @@</span><br><span> #include <pc80/mc146818rtc.h></span><br><span> #include "82870.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void p64h2_pcix_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void p64h2_pcix_init(struct device *dev)</span><br><span> {</span><br><span>    u32 dword;</span><br><span>   u8 byte;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26258">change 26258</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26258"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I751b72733de2e3bf3aebd1bc85dc83ec1c406faa </div>
<div style="display:none"> Gerrit-Change-Number: 26258 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>