<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26257">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/i82801jx: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I37be7672c88b28180d7d4b46928ebed8472ec020<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/i82801jx/hdaudio.c<br>M src/southbridge/intel/i82801jx/i82801jx.c<br>M src/southbridge/intel/i82801jx/lpc.c<br>M src/southbridge/intel/i82801jx/pci.c<br>M src/southbridge/intel/i82801jx/pcie.c<br>M src/southbridge/intel/i82801jx/sata.c<br>M src/southbridge/intel/i82801jx/smbus.c<br>M src/southbridge/intel/i82801jx/thermal.c<br>M src/southbridge/intel/i82801jx/usb_ehci.c<br>9 files changed, 32 insertions(+), 32 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/26257/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c</span><br><span>index c75eee7..f2272d0 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/hdaudio.c</span><br><span>+++ b/src/southbridge/intel/i82801jx/hdaudio.c</span><br><span>@@ -287,7 +287,7 @@</span><br><span>        }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void azalia_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>      if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c</span><br><span>index 644524d..66cc7d9 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/i82801jx.c</span><br><span>+++ b/src/southbridge/intel/i82801jx/i82801jx.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> </span><br><span> typedef struct southbridge_intel_i82801jx_config config_t;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i82801jx_enable_device(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801jx_enable_device(struct device *dev)</span><br><span> {</span><br><span>     u32 reg32;</span><br><span> </span><br><span>@@ -51,7 +51,7 @@</span><br><span> </span><br><span> static void i82801jx_pcie_init(const config_t *const info)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-       device_t pciePort[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *pciePort[6];</span><br><span>  int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */</span><br><span>        u32 reg32;</span><br><span> </span><br><span>@@ -86,7 +86,7 @@</span><br><span> </span><br><span>       /* Set slot implemented, slot number and slot power limits. */</span><br><span>       for (i = 0; i < 6; ++i) {</span><br><span style="color: hsl(0, 100%, 40%);">-            const device_t dev = pciePort[i];</span><br><span style="color: hsl(120, 100%, 40%);">+             const struct device *dev = pciePort[i];</span><br><span>              u32 xcap = pci_read_config32(dev, D28Fx_XCAP);</span><br><span>               if (info->pcie_slot_implemented & (1 << i))</span><br><span>                     xcap |=  PCI_EXP_FLAGS_SLOT;</span><br><span>@@ -115,10 +115,10 @@</span><br><span> </span><br><span> static void i82801jx_ehci_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-   const device_t pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7));</span><br><span style="color: hsl(120, 100%, 40%);">+       const struct device *pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7));</span><br><span>        if (!pciEHCI1)</span><br><span>               die("EHCI controller (00:1d.7) not listed in devicetree.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- const device_t pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7));</span><br><span style="color: hsl(120, 100%, 40%);">+       const struct device *pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7));</span><br><span>        if (!pciEHCI2)</span><br><span>               die("EHCI controller (00:1a.7) not listed in devicetree.\n");</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c</span><br><span>index c631da9..ff86f0f 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/lpc.c</span><br><span>+++ b/src/southbridge/intel/i82801jx/lpc.c</span><br><span>@@ -91,9 +91,9 @@</span><br><span>  * 0x80 - The PIRQ is not routed.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i82801jx_pirq_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801jx_pirq_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-       device_t irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+     struct device *irq_dev;</span><br><span> </span><br><span>  /* Interrupt 11 is not used by legacy devices and so can always be used</span><br><span>       * for PCI interrupts. Full legacy IRQ routing is complicated and hard</span><br><span>@@ -134,7 +134,7 @@</span><br><span>         }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i82801jx_gpi_routing(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801jx_gpi_routing(struct device *dev)</span><br><span> {</span><br><span>  /* Get the chip configuration */</span><br><span>     config_t *config = dev->chip_info;</span><br><span>@@ -163,7 +163,7 @@</span><br><span>  pci_write_config32(dev, D31F0_GPIO_ROUT, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i82801jx_power_options(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801jx_power_options(struct device *dev)</span><br><span> {</span><br><span>       u8 reg8;</span><br><span>     u16 reg16, pmbase;</span><br><span>@@ -295,7 +295,7 @@</span><br><span>     outl(reg32, pmbase + 0x10);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i82801jx_configure_cstates(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801jx_configure_cstates(struct device *dev)</span><br><span> {</span><br><span>    u8 reg8;</span><br><span> </span><br><span>@@ -501,7 +501,7 @@</span><br><span> </span><br><span> void acpi_fill_fadt(acpi_fadt_t *fadt)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-   device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+  struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));</span><br><span>   config_t *chip = dev->chip_info;</span><br><span>  u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;</span><br><span> </span><br><span>@@ -616,7 +616,7 @@</span><br><span>            fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i82801jx_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801jx_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span>       int i, io_index = 0;</span><br><span>         /*</span><br><span>@@ -687,7 +687,7 @@</span><br><span>     }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>    if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -698,7 +698,7 @@</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_inject_dsdt(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_inject_dsdt(struct device *dev)</span><br><span> {</span><br><span>    global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));</span><br><span> </span><br><span>@@ -720,9 +720,9 @@</span><br><span>        }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_fill_ssdt(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_fill_ssdt(struct device *device)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-     device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+   struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span>    config_t *chip = dev->chip_info;</span><br><span> </span><br><span>      intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);</span><br><span>diff --git a/src/southbridge/intel/i82801jx/pci.c b/src/southbridge/intel/i82801jx/pci.c</span><br><span>index 2262c91..cfafda0 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/pci.c</span><br><span>+++ b/src/southbridge/intel/i82801jx/pci.c</span><br><span>@@ -43,7 +43,7 @@</span><br><span>    pci_write_config16(dev, PCI_SEC_STATUS, reg16);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>      /* NOTE: 0x54 is not the default position! */</span><br><span>        if (!vendor || !device) {</span><br><span>diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c</span><br><span>index 01f65de..a000ff8 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/pcie.c</span><br><span>+++ b/src/southbridge/intel/i82801jx/pcie.c</span><br><span>@@ -94,7 +94,7 @@</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>  /* NOTE: 0x94 is not the default position! */</span><br><span>        if (!vendor || !device) {</span><br><span>@@ -106,7 +106,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pciexp_scan_bridge(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pciexp_scan_bridge(struct device *dev)</span><br><span> {</span><br><span>      struct southbridge_intel_i82801jx_config *config = dev->chip_info;</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c</span><br><span>index 9fe1f9e..2d70a6c 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/sata.c</span><br><span>+++ b/src/southbridge/intel/i82801jx/sata.c</span><br><span>@@ -208,7 +208,7 @@</span><br><span>     pci_write_config32(dev, 0x94, sclkcg);</span><br><span> </span><br><span>   if (is_mobile && config->sata_traffic_monitor) {</span><br><span style="color: hsl(0, 100%, 40%);">-             const device_t lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+                const struct device *lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));</span><br><span>                 if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF)</span><br><span>                                                   >> 3) & 3) == 3) {</span><br><span>                         u8 reg8 = pci_read_config8(dev, 0x9c);</span><br><span>@@ -224,7 +224,7 @@</span><br><span>         sata_program_indexed(dev, is_mobile);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_enable(struct device *dev)</span><br><span> {</span><br><span>        /* Get the chip configuration */</span><br><span>     const config_t *const config = dev->chip_info;</span><br><span>@@ -251,7 +251,7 @@</span><br><span>      pci_write_config16(dev, 0x90, map);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>        if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c</span><br><span>index 9ccff41..a1dc2a5 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/smbus.c</span><br><span>+++ b/src/southbridge/intel/i82801jx/smbus.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "i82801jx.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_smbus_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_smbus_init(struct device *dev)</span><br><span> {</span><br><span>   u16 reg16;</span><br><span> </span><br><span>@@ -35,7 +35,7 @@</span><br><span>   pci_write_config16(dev, 0x80, reg16);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, u8 address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span> {</span><br><span>        u16 device;</span><br><span>  struct resource *res;</span><br><span>@@ -48,7 +48,7 @@</span><br><span>    return do_smbus_read_byte(res->base, device, address);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)</span><br><span> {</span><br><span>  u16 device;</span><br><span>  struct resource *res;</span><br><span>@@ -61,7 +61,7 @@</span><br><span>    return do_smbus_write_byte(res->base, device, address, val);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf)</span><br><span> {</span><br><span>        u16 device;</span><br><span>  struct resource *res;</span><br><span>@@ -73,7 +73,7 @@</span><br><span>    return do_smbus_block_write(res->base, device, cmd, bytes, buf);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buf)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf)</span><br><span> {</span><br><span>  u16 device;</span><br><span>  struct resource *res;</span><br><span>@@ -92,7 +92,7 @@</span><br><span>    .block_write    = lsmbus_block_write,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void smbus_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>   if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -107,7 +107,7 @@</span><br><span>       .set_subsystem    = smbus_set_subsystem,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void smbus_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void smbus_read_resources(struct device *dev)</span><br><span> {</span><br><span>  struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);</span><br><span>        res->base = SMBUS_IO_BASE;</span><br><span>diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c</span><br><span>index a5d5bed..b0b17de 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/thermal.c</span><br><span>+++ b/src/southbridge/intel/i82801jx/thermal.c</span><br><span>@@ -50,7 +50,7 @@</span><br><span>       pci_write_config32(dev, 0x10, 0);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void thermal_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void thermal_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>    if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c</span><br><span>index d5a0d97..23d5d4a 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/usb_ehci.c</span><br><span>+++ b/src/southbridge/intel/i82801jx/usb_ehci.c</span><br><span>@@ -33,7 +33,7 @@</span><br><span>        printk(BIOS_DEBUG, "done.\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>   u8 access_cntl;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26257">change 26257</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26257"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I37be7672c88b28180d7d4b46928ebed8472ec020 </div>
<div style="display:none"> Gerrit-Change-Number: 26257 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>