<p><a href="https://review.coreboot.org/26196">View Change</a></p><p>5 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26196/1/src/northbridge/intel/haswell/gma.c">File src/northbridge/intel/haswell/gma.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26196/1/src/northbridge/intel/haswell/gma.c@490">Patch Set #1, Line 490:</a> <code style="font-family:monospace,monospace">static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">overline</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26196/1/src/northbridge/intel/haswell/minihd.c">File src/northbridge/intel/haswell/minihd.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26196/1/src/northbridge/intel/haswell/minihd.c@106">Patch Set #1, Line 106:</a> <code style="font-family:monospace,monospace">static void minihd_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">overline</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26196/1/src/northbridge/intel/haswell/northbridge.c">File src/northbridge/intel/haswell/northbridge.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26196/1/src/northbridge/intel/haswell/northbridge.c@36">Patch Set #1, Line 36:</a> <code style="font-family:monospace,monospace">static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">overline</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26196/1/src/northbridge/intel/haswell/northbridge.c@109">Patch Set #1, Line 109:</a> <code style="font-family:monospace,monospace">static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">overline</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26196/1/src/northbridge/intel/haswell/northbridge.c@409">Patch Set #1, Line 409:</a> <code style="font-family:monospace,monospace">static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">overline</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/26196">change 26196</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26196"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: comment </div>
<div style="display:none"> Gerrit-Change-Id: I10fb736a7406a6571dffce883fb82c2711526762 </div>
<div style="display:none"> Gerrit-Change-Number: 26196 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-CC: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Comment-Date: Thu, 10 May 2018 10:12:47 +0000 </div>
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