<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26195">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/fsp_sandybridge: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: Id3289c891e8a81c750fc3f5fad0fd16c0f2702fe<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/intel/fsp_sandybridge/acpi.c<br>M src/northbridge/intel/fsp_sandybridge/gma.c<br>M src/northbridge/intel/fsp_sandybridge/northbridge.c<br>3 files changed, 12 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/26195/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c</span><br><span>index 28df4a5..8422771 100644</span><br><span>--- a/src/northbridge/intel/fsp_sandybridge/acpi.c</span><br><span>+++ b/src/northbridge/intel/fsp_sandybridge/acpi.c</span><br><span>@@ -23,7 +23,7 @@</span><br><span> </span><br><span> unsigned long acpi_fill_mcfg(unsigned long current)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  u32 pciexbar = 0;</span><br><span>    u32 pciexbar_reg;</span><br><span>    int max_buses;</span><br><span>diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c</span><br><span>index 1433a01..18f1148 100644</span><br><span>--- a/src/northbridge/intel/fsp_sandybridge/gma.c</span><br><span>+++ b/src/northbridge/intel/fsp_sandybridge/gma.c</span><br><span>@@ -66,7 +66,7 @@</span><br><span>          gnvs_ptr->aslb = aslb;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>    if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -80,7 +80,7 @@</span><br><span> const struct i915_gpu_controller_info *</span><br><span> intel_gma_get_controller_info(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-     device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));</span><br><span style="color: hsl(120, 100%, 40%);">+    struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0));</span><br><span>     if (!dev) {</span><br><span>          return NULL;</span><br><span>         }</span><br><span>@@ -88,7 +88,7 @@</span><br><span>        return &chip->gfx;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gma_ssdt(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gma_ssdt(struct device *device)</span><br><span> {</span><br><span>    const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();</span><br><span>        if (!gfx) {</span><br><span>diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c</span><br><span>index 2dfe44d..17b0571 100644</span><br><span>--- a/src/northbridge/intel/fsp_sandybridge/northbridge.c</span><br><span>+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c</span><br><span>@@ -63,7 +63,7 @@</span><br><span> </span><br><span> static int get_pcie_bar(u32 *base)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  u32 pciexbar_reg;</span><br><span> </span><br><span>        *base = 0;</span><br><span>@@ -99,7 +99,7 @@</span><br><span>       mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_domain_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_domain_set_resources(struct device *dev)</span><br><span> {</span><br><span>       uint64_t tom, me_base, touud;</span><br><span>        uint32_t tseg_base, uma_size, tolud;</span><br><span>@@ -235,7 +235,7 @@</span><br><span>   .scan_bus         = pci_domain_scan_bus,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_read_resources(struct device *dev)</span><br><span> {</span><br><span>        u32 pcie_config_base;</span><br><span>        int buses;</span><br><span>@@ -249,7 +249,7 @@</span><br><span>     }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>        if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -274,7 +274,7 @@</span><br><span>       printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u32 northbridge_get_base_reg(device_t dev, int reg)</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 northbridge_get_base_reg(struct device *dev, int reg)</span><br><span> {</span><br><span>      u32 value;</span><br><span> </span><br><span>@@ -286,7 +286,7 @@</span><br><span> </span><br><span> u32 northbridge_get_tseg_base(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+       const struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));</span><br><span> </span><br><span>    return northbridge_get_base_reg(dev, TSEG);</span><br><span> }</span><br><span>@@ -328,7 +328,7 @@</span><br><span>       .device = 0x0154, /* Ivy bridge */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void cpu_bus_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void cpu_bus_init(struct device *dev)</span><br><span> {</span><br><span>        initialize_cpus(dev->link_list);</span><br><span> }</span><br><span>@@ -341,7 +341,7 @@</span><br><span>       .scan_bus         = 0,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_dev(struct device *dev)</span><br><span> {</span><br><span>        /* Set the operations if it is a special bus type */</span><br><span>         if (dev->path.type == DEVICE_PATH_DOMAIN) {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26195">change 26195</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26195"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id3289c891e8a81c750fc3f5fad0fd16c0f2702fe </div>
<div style="display:none"> Gerrit-Change-Number: 26195 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>