<p>Youness Alaoui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26184">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">purism/librem_bdl: Add support for Librem 15 v2<br><br>Adding new librem_bdl variant for the Librem 15 v2, which is very similar<br>to Librem 13 v1, with the following differences:<br>- SATA ports 0 and 1 instead of 0 and 3<br>- SATA DTLE IOBP value is 7 instead of 9 for port 0<br>- There is no LAN device<br>- There are two SODIMM slots, and DQs are interleaved<br>- USB ports are different<br><br>Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b<br>Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm><br>---<br>M src/mainboard/purism/librem_bdl/Kconfig<br>M src/mainboard/purism/librem_bdl/Kconfig.name<br>A src/mainboard/purism/librem_bdl/variants/librem15v2/board_info.txt<br>A src/mainboard/purism/librem_bdl/variants/librem15v2/devicetree.cb<br>A src/mainboard/purism/librem_bdl/variants/librem15v2/pei_data.c<br>5 files changed, 160 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/26184/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/purism/librem_bdl/Kconfig b/src/mainboard/purism/librem_bdl/Kconfig</span><br><span>index 63863ca..910be05 100644</span><br><span>--- a/src/mainboard/purism/librem_bdl/Kconfig</span><br><span>+++ b/src/mainboard/purism/librem_bdl/Kconfig</span><br><span>@@ -13,10 +13,12 @@</span><br><span> config VARIANT_DIR</span><br><span> string</span><br><span> default "librem13v1" if BOARD_PURISM_LIBREM13_V1</span><br><span style="color: hsl(120, 100%, 40%);">+ default "librem15v2" if BOARD_PURISM_LIBREM15_V2</span><br><span> </span><br><span> config DEVICETREE</span><br><span> string</span><br><span> default "variants/librem13v1/devicetree.cb" if BOARD_PURISM_LIBREM13_V1</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/librem15v2/devicetree.cb" if BOARD_PURISM_LIBREM15_V2</span><br><span> </span><br><span> config DRIVERS_PS2_KEYBOARD</span><br><span> def_bool y</span><br><span>@@ -54,14 +56,17 @@</span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span> default "Librem 13 v1" if BOARD_PURISM_LIBREM13_V1</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Librem 15 v2" if BOARD_PURISM_LIBREM15_V2</span><br><span> </span><br><span> config MAINBOARD_FAMILY</span><br><span> string</span><br><span> default "Librem 13" if BOARD_PURISM_LIBREM13_V1</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Librem 15" if BOARD_PURISM_LIBREM15_V2</span><br><span> </span><br><span> config MAINBOARD_VERSION</span><br><span> string</span><br><span> default "1.0" if BOARD_PURISM_LIBREM13_V1</span><br><span style="color: hsl(120, 100%, 40%);">+ default "2.0" if BOARD_PURISM_LIBREM15_V2</span><br><span> </span><br><span> config MAX_CPUS</span><br><span> int</span><br><span>@@ -79,6 +84,8 @@</span><br><span> </span><br><span> config VGA_BIOS_ID</span><br><span> string</span><br><span style="color: hsl(0, 100%, 40%);">- default "8086,1616"</span><br><span style="color: hsl(120, 100%, 40%);">+ default "8086,1616" if BOARD_PURISM_LIBREM13_V1</span><br><span style="color: hsl(120, 100%, 40%);">+ default "8086,162b" if BOARD_PURISM_LIBREM15_V2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> </span><br><span> endif</span><br><span>diff --git a/src/mainboard/purism/librem_bdl/Kconfig.name b/src/mainboard/purism/librem_bdl/Kconfig.name</span><br><span>index 498c6ef..e0cbed4 100644</span><br><span>--- a/src/mainboard/purism/librem_bdl/Kconfig.name</span><br><span>+++ b/src/mainboard/purism/librem_bdl/Kconfig.name</span><br><span>@@ -1,3 +1,7 @@</span><br><span> config BOARD_PURISM_LIBREM13_V1</span><br><span> bool "Librem 13 v1"</span><br><span> select BOARD_PURISM_BASEBOARD_LIBREM_BDL</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_PURISM_LIBREM15_V2</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Librem 15 v2"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_PURISM_BASEBOARD_LIBREM_BDL</span><br><span>diff --git a/src/mainboard/purism/librem_bdl/variants/librem15v2/board_info.txt b/src/mainboard/purism/librem_bdl/variants/librem15v2/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..953e92e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/purism/librem_bdl/variants/librem15v2/board_info.txt</span><br><span>@@ -0,0 +1,9 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: laptop</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor name: Purism</span><br><span style="color: hsl(120, 100%, 40%);">+Board name: Librem 15 v2</span><br><span style="color: hsl(120, 100%, 40%);">+Board URL: https://web.archive.org/web/20160529052744/https://puri.sm/librem-15/</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: SOIC8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2015</span><br><span>diff --git a/src/mainboard/purism/librem_bdl/variants/librem15v2/devicetree.cb b/src/mainboard/purism/librem_bdl/variants/librem15v2/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..3e83d3f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/purism/librem_bdl/variants/librem15v2/devicetree.cb</span><br><span>@@ -0,0 +1,75 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/broadwell</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable eDP Hotplug with 6ms pulse</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_d_hotplug" = "0x06"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable DDI1 Hotplug with 6ms pulse</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_b_hotplug" = "0x06"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set backlight PWM values for eDP</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_cpu_backlight" = "0x00000200"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_pch_backlight" = "0x04000200"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Panel and configure power delays</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_port_select" = "1" # eDP</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_cycle_delay" = "6" # 500ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_up_delay" = "2000" # 200ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_down_delay" = "500" # 50ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command ranges are in 0x380-0x383 & 0x80-0x8f</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00000381"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c0081"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Port 0 is HDD</span><br><span style="color: hsl(120, 100%, 40%);">+ # Port 1 is M.2 NGFF</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x3"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Port tuning for link stability</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port0_gen3_dtle" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port1_gen3_dtle" = "9"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port2_gen3_dtle" = "9"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port3_gen3_dtle" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # host bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # vga controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.0 on end # mini-hd audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.0 off end # Smart Sound Audio DSP</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # USB3 XHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 off end # Serial I/O DMA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 off end # I2C0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 off end # I2C1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 off end # GSPI0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.4 off end # GSPI1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.5 off end # UART0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.6 off end # UART1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 off end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 off end # SDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on end # High Definition Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCIe Port #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCIe Port #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCIe Port #3 - LAN</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on end # PCIe Port #4 - WiFi</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCIe Port #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # USB2 EHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/purism/librem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c09.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # SATA Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/purism/librem_bdl/variants/librem15v2/pei_data.c b/src/mainboard/purism/librem_bdl/variants/librem15v2/pei_data.c</span><br><span>new file mode 100644</span><br><span>index 0000000..83de020</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/purism/librem_bdl/variants/librem15v2/pei_data.c</span><br><span>@@ -0,0 +1,64 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pei_data.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pei_wrapper.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_pei_data(struct pei_data *pei_data)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data->ec_present = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data->dq_pins_interleaved = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* One DIMM slot */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data->dimm_channel0_disabled = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data->dimm_channel1_disabled = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data->spd_addresses[0] = 0xa0;</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data->spd_addresses[2] = 0xa4;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P1: Right Side Port (USB2) */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_BACK_PANEL);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P2: Right Side Port (USB2) */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data_usb2_port(pei_data, 1, 0x0080, 1, USB_OC_PIN_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_BACK_PANEL);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P3: Left Side Port (USB2 only) */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_BACK_PANEL);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P4: Left Side Port (USB2 only) */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data_usb2_port(pei_data, 3, 0x0080, 1, USB_OC_PIN_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_BACK_PANEL);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P5: Empty */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data_usb2_port(pei_data, 4, 0x0080, 0, USB_OC_PIN_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_BACK_PANEL);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P6: Bluetooth */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data_usb2_port(pei_data, 5, 0x0080, 1, USB_OC_PIN_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_SKIP);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P7: Camera */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data_usb2_port(pei_data, 6, 0x0080, 1, USB_OC_PIN_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_SKIP);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P8: SD Card */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data_usb2_port(pei_data, 7, 0x0080, 1, USB_OC_PIN_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_BACK_PANEL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P1: Right Side Port (USB3) */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P2: Right Side Port (USB3) */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P3: Empty */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P4: Empty */</span><br><span style="color: hsl(120, 100%, 40%);">+ pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26184">change 26184</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26184"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b </div>
<div style="display:none"> Gerrit-Change-Number: 26184 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Youness Alaoui <snifikino@gmail.com> </div>