<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26148">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/fsp: Update Cannonlake FSP header<br><br>Update Cannonlake FSP header to version 7.x.2E.50, the following changes<br>were made,<br>Memory Init UPD:<br> 1.Add GDXC configuration options.<br> 2.Remove some internal graphics memory selections.<br> 2.Remove Fixed mid option for SaGv.<br> 3.Add DualDimm per channel board type.<br> 4.Remove PEG IMR options.<br>Silicon Init UPD:<br> 1.Add CD clock selections of 675MHz.<br> 2.Remove Pcode PreWake/Rampup/RampDn time selections.<br> 3.Remove C3 state demotion/unDemotion selections.<br><br>BUG=None<br>TEST=Build and boot up on meowth platform.<br><br>Change-Id: I08ffb14df9f32089dbf44fa5bd3fc58a5bedb90d<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>2 files changed, 92 insertions(+), 60 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/26148/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h</span><br><span>index 74cc672..1bac0b8 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h</span><br><span>@@ -182,9 +182,15 @@</span><br><span> **/</span><br><span> UINT8 ProbelessTrace;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00A3</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00A3 - GDXC IOT SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of IOT and MOT is in 8 MB chunks</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace0[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GdxcIotSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00A4 - GDXC MOT SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of IOT and MOT is in 8 MB chunks</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GdxcMotSize;</span><br><span> </span><br><span> /** Offset 0x00A5 - Enable SMBus</span><br><span> Enable/disable SMBus controller.</span><br><span>@@ -244,9 +250,7 @@</span><br><span> </span><br><span> /** Offset 0x00B8 - Internal Graphics Pre-allocated Memory</span><br><span> Size of memory preallocated for internal graphics.</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00:0MB, 0x01:32MB, 0x02:64MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xFD:56MB, 0xFE:60MB</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00:0 MB, 0x01:32 MB, 0x02:64 MB</span><br><span> **/</span><br><span> UINT8 IgdDvmt50PreAlloc;</span><br><span> </span><br><span>@@ -272,14 +276,14 @@</span><br><span> /** Offset 0x00BC - SA GV</span><br><span> System Agent dynamic frequency support and when enabled memory will be training</span><br><span> at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,</span><br><span style="color: hsl(0, 100%, 40%);">- 2=FixedMid, 3=FixedHigh, and 4=Enabled.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ 2=FixedHigh, and 3=Enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled</span><br><span> **/</span><br><span> UINT8 SaGv;</span><br><span> </span><br><span> /** Offset 0x00BD</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace1;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace0;</span><br><span> </span><br><span> /** Offset 0x00BE - DDR Frequency Limit</span><br><span> Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk,</span><br><span>@@ -329,7 +333,7 @@</span><br><span> </span><br><span> /** Offset 0x00C8</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace2[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace1[16];</span><br><span> </span><br><span> /** Offset 0x00D8 - SPD Profile Selected</span><br><span> Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP</span><br><span>@@ -488,7 +492,7 @@</span><br><span> </span><br><span> /** Offset 0x00F8</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace3[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace2[4];</span><br><span> </span><br><span> /** Offset 0x00FC - Enable Intel HD Audio (Azalia)</span><br><span> 0: Disable, 1: Enable (Default) Azalia controller</span><br><span>@@ -510,7 +514,7 @@</span><br><span> </span><br><span> /** Offset 0x00FF</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace4;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace3;</span><br><span> </span><br><span> /** Offset 0x0100 - HECI1 BAR address</span><br><span> BAR address of HECI1</span><br><span>@@ -681,7 +685,7 @@</span><br><span> </span><br><span> /** Offset 0x0125</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace5[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace4[3];</span><br><span> </span><br><span> /** Offset 0x0128 - DMI Gen3 Root port preset values per lane</span><br><span> Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane</span><br><span>@@ -720,7 +724,7 @@</span><br><span> </span><br><span> /** Offset 0x0146</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace6[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace5[2];</span><br><span> </span><br><span> /** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control</span><br><span> Range: 0-15, 12 is default for each bundle, must be specified based upon platform design</span><br><span>@@ -957,7 +961,7 @@</span><br><span> </span><br><span> /** Offset 0x0207</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace7;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace6;</span><br><span> </span><br><span> /** Offset 0x0208 - Maximum clr turbo ratio override</span><br><span> Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the</span><br><span>@@ -2275,21 +2279,18 @@</span><br><span> **/</span><br><span> UINT8 EnBER;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x050F - PEG IMR support</span><br><span style="color: hsl(0, 100%, 40%);">- This option configures the IMR support for PEG.(def=Disable)</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x050F - Dual Dimm Per-Channel Board Type</span><br><span style="color: hsl(120, 100%, 40%);">+ Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used</span><br><span style="color: hsl(120, 100%, 40%);">+ to limit maximum frequency for some SKUs.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:1DPC, 1:2DPC</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DualDimmPerChannelBoardType;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0510 - CFL Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved FspmConfig CFL</span><br><span> $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PegImrEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0510 - PEG IMR size</span><br><span style="color: hsl(0, 100%, 40%);">- The size of IMR to be allocated for PEG EndPoint device</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PegImrSize;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0512 - PEG Root Port Selection</span><br><span style="color: hsl(0, 100%, 40%);">- The Root Port for which the IMR to be allocated</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PegImrRpSelection;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspmUpdCfl[3];</span><br><span> </span><br><span> /** Offset 0x0513 - Memory Test on Warm Boot</span><br><span> Run Base Memory Test on Warm Boot</span><br><span>@@ -2524,7 +2525,7 @@</span><br><span> </span><br><span> /** Offset 0x0579</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace10;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace9;</span><br><span> </span><br><span> /** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization</span><br><span> Range: 0-65535, default is 1000. @warning Do not change from the default</span><br><span>@@ -2799,7 +2800,7 @@</span><br><span> </span><br><span> /** Offset 0x051F</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace9;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace8;</span><br><span> </span><br><span> /** Offset 0x0520</span><br><span> **/</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>index 4daf891..12c6e44 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>@@ -717,8 +717,8 @@</span><br><span> UINT8 PavpEnable;</span><br><span> </span><br><span> /** Offset 0x0217 - CdClock Frequency selection</span><br><span style="color: hsl(0, 100%, 40%);">- 0=168 Mhz, 1=336 Mhz, 2(Default)=528 Mhz</span><br><span style="color: hsl(0, 100%, 40%);">- 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=168 Mhz, 1=336 Mhz, 2=528 Mhz, 3(Default)=675 Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz, 3: 675 Mhz</span><br><span> **/</span><br><span> UINT8 CdClock;</span><br><span> </span><br><span>@@ -907,7 +907,9 @@</span><br><span> UINT8 PsysOffset;</span><br><span> </span><br><span> /** Offset 0x02A2 - Acoustic Noise Mitigation feature</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program</span><br><span style="color: hsl(120, 100%, 40%);">+ slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.<b>0:</span><br><span style="color: hsl(120, 100%, 40%);">+ Disabled</b>; 1: Enabled</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 AcousticNoiseMitigation;</span><br><span>@@ -1100,15 +1102,32 @@</span><br><span> **/</span><br><span> UINT32 VrPowerDeliveryDesign;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0328 - ReservedCpuPostMemProduction</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0328 - Pre Wake Randomization time</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization</span><br><span style="color: hsl(120, 100%, 40%);">+ time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0-255 <b>0</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PreWake;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0329 - Ramp Up Randomization time</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization</span><br><span style="color: hsl(120, 100%, 40%);">+ time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range</span><br><span style="color: hsl(120, 100%, 40%);">+ 0-255 <b>0</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RampUp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x032A - Ramp Down Randomization time</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization</span><br><span style="color: hsl(120, 100%, 40%);">+ time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range</span><br><span style="color: hsl(120, 100%, 40%);">+ 0-255 <b>0</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RampDown;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x032B - ReservedCpuPostMemProduction</span><br><span> Reserved for CPU Post-Mem Production</span><br><span> $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedCpuPostMemProduction[1];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0329</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace10[29];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedCpuPostMemProduction[27];</span><br><span> </span><br><span> /** Offset 0x0346 - Enable DMI ASPM</span><br><span> Deprecated.</span><br><span>@@ -1151,7 +1170,7 @@</span><br><span> </span><br><span> /** Offset 0x0367</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace11;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace10;</span><br><span> </span><br><span> /** Offset 0x0368 - VC Type</span><br><span> Virtual Channel Type Select: 0: VC0, 1: VC1.</span><br><span>@@ -1192,7 +1211,7 @@</span><br><span> </span><br><span> /** Offset 0x036E</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace12[15];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace11[15];</span><br><span> </span><br><span> /** Offset 0x037D - Enable PCH Io Apic Entry 24-119</span><br><span> 0: Disable; 1: Enable.</span><br><span>@@ -1207,7 +1226,7 @@</span><br><span> </span><br><span> /** Offset 0x037F</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace13;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace12;</span><br><span> </span><br><span> /** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned</span><br><span> 0: Disable; 1: Enable.</span><br><span>@@ -1307,7 +1326,7 @@</span><br><span> </span><br><span> /** Offset 0x0390</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace14[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace13[3];</span><br><span> </span><br><span> /** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK</span><br><span> Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region</span><br><span>@@ -1401,7 +1420,7 @@</span><br><span> </span><br><span> /** Offset 0x04E6</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace15[24];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace14[24];</span><br><span> </span><br><span> /** Offset 0x04FE - PCIE RP Pcie Speed</span><br><span> Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:</span><br><span>@@ -1427,7 +1446,7 @@</span><br><span> </span><br><span> /** Offset 0x055E</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace16[106];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace15[106];</span><br><span> </span><br><span> /** Offset 0x05C8 - PCIE RP Aspm</span><br><span> The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is</span><br><span>@@ -1486,7 +1505,7 @@</span><br><span> </span><br><span> /** Offset 0x0664</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace17;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace16;</span><br><span> </span><br><span> /** Offset 0x0665 - PCIE Compliance Test Mode</span><br><span> Compliance Test Mode shall be enabled when using Compliance Load Board.</span><br><span>@@ -1503,7 +1522,7 @@</span><br><span> </span><br><span> /** Offset 0x0667</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace18[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace17[2];</span><br><span> </span><br><span> /** Offset 0x0669 - PCH Pm PME_B0_S5_DIS</span><br><span> When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.</span><br><span>@@ -1529,7 +1548,7 @@</span><br><span> </span><br><span> /** Offset 0x066F</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace19;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace18;</span><br><span> </span><br><span> /** Offset 0x0670 - PCH Pm Wol Enable Override</span><br><span> Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.</span><br><span>@@ -1618,7 +1637,7 @@</span><br><span> </span><br><span> /** Offset 0x067D</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace20[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace19[3];</span><br><span> </span><br><span> /** Offset 0x0680 - PCH Pm Lpc Clock Run</span><br><span> This member describes whether or not the LPC ClockRun feature of PCH should be enabled.</span><br><span>@@ -1652,7 +1671,7 @@</span><br><span> </span><br><span> /** Offset 0x0685</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace21;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace20;</span><br><span> </span><br><span> /** Offset 0x0686 - PCH Pm Disable Native Power Button</span><br><span> Power button native mode disable.</span><br><span>@@ -1692,7 +1711,7 @@</span><br><span> </span><br><span> /** Offset 0x068C</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace22;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace21;</span><br><span> </span><br><span> /** Offset 0x068D - PCH Sata Pwr Opt Enable</span><br><span> SATA Power Optimizer on PCH side.</span><br><span>@@ -1881,7 +1900,7 @@</span><br><span> </span><br><span> /** Offset 0x0700</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace23;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace22;</span><br><span> </span><br><span> /** Offset 0x0701 - PcdSerialIoUart0PinMuxing</span><br><span> Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled.</span><br><span>@@ -1891,7 +1910,7 @@</span><br><span> </span><br><span> /** Offset 0x0702</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace24[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace23[1];</span><br><span> </span><br><span> /** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines</span><br><span> Enables UART hardware flow control, CTS and RTS linesh.</span><br><span>@@ -2164,7 +2183,7 @@</span><br><span> </span><br><span> /** Offset 0x0753</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace25;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace24;</span><br><span> </span><br><span> /** Offset 0x0754 - Pch PCIE device override table pointer</span><br><span> The PCIe device table is being used to override PCIe device ASPM settings. This</span><br><span>@@ -2343,7 +2362,7 @@</span><br><span> UINT8 PmSupport;</span><br><span> </span><br><span> /** Offset 0x07BC - Enable/Disable CdynmaxClamp</span><br><span style="color: hsl(0, 100%, 40%);">- Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 CdynmaxClampEnable;</span><br><span>@@ -2465,7 +2484,7 @@</span><br><span> /** Offset 0x07D8 - TCC Activation Offset</span><br><span> TCC Activation Offset. Offset from factory set TCC activation temperature at which</span><br><span> the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation</span><br><span style="color: hsl(0, 100%, 40%);">- Temperature, in volts.For Y SKU, the recommended default for this policy is <b>10</b>,</span><br><span style="color: hsl(120, 100%, 40%);">+ Temperature, in volts.For Y SKU, the recommended default for this policy is <b>15</b>,</span><br><span> For all other SKUs the recommended default are <b>0</b></span><br><span> **/</span><br><span> UINT8 TccActivationOffset;</span><br><span>@@ -2792,8 +2811,8 @@</span><br><span> UINT8 CstateLatencyControl5TimeUnit;</span><br><span> </span><br><span> /** Offset 0x0819 - Interrupt Redirection Mode Select</span><br><span style="color: hsl(0, 100%, 40%);">- Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7:</span><br><span style="color: hsl(0, 100%, 40%);">- No change.</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:</span><br><span style="color: hsl(120, 100%, 40%);">+ PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.</span><br><span> **/</span><br><span> UINT8 PpmIrmSetting;</span><br><span> </span><br><span>@@ -3040,11 +3059,23 @@</span><br><span> **/</span><br><span> UINT8 MaxRingRatioLimit;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08A5 - ReservedCpuPostMemTest</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C3StateAutoDemotion;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C3StateUnDemotion;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A7 - ReservedCpuPostMemTest</span><br><span> Reserved for CPU Post-Mem Test</span><br><span> $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedCpuPostMemTest[21];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedCpuPostMemTest[19];</span><br><span> </span><br><span> /** Offset 0x08BA - SgxSinitDataFromTpm</span><br><span> SgxSinitDataFromTpm default values</span><br><span>@@ -3194,7 +3225,7 @@</span><br><span> </span><br><span> /** Offset 0x0A61</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace26[17];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace25[17];</span><br><span> </span><br><span> /** Offset 0x0A72 - Skip POSTBOOT SAI</span><br><span> Deprecated</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26148">change 26148</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26148"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I08ffb14df9f32089dbf44fa5bd3fc58a5bedb90d </div>
<div style="display:none"> Gerrit-Change-Number: 26148 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>