<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26149">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Intel haswell/broadwell: CPL2 method doesn't use any arguments<br><br>- Update the CPL2 method to not take any arguments.<br>- Don't pass the Method any values.<br><br>Change-Id: I7fb96fc7f22a387d796752dcfce4639293c45e5e<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/northbridge/intel/haswell/acpi/hostbridge.asl<br>M src/soc/intel/broadwell/acpi/ctdp.asl<br>2 files changed, 6 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/26149/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl</span><br><span>index 2565851..ed2284a 100644</span><br><span>--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl</span><br><span>+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl</span><br><span>@@ -172,7 +172,7 @@</span><br><span>         }</span><br><span> </span><br><span>        /* Calculate PL2 based on chip type */</span><br><span style="color: hsl(0, 100%, 40%);">-  Method (CPL2, 1, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+       Method (CPL2, 0, NotSerialized)</span><br><span>      {</span><br><span>            If (\ISLP ()) {</span><br><span>                      /* Haswell ULT PL2 = 25W */</span><br><span>@@ -207,7 +207,7 @@</span><br><span>            PPCN ()</span><br><span> </span><br><span>          /* Set PL2 */</span><br><span style="color: hsl(0, 100%, 40%);">-           Store (CPL2 (CTDD), PL2V)</span><br><span style="color: hsl(120, 100%, 40%);">+             Store (CPL2 (), PL2V)</span><br><span> </span><br><span>            /* Set PL1 */</span><br><span>                Store (CTDD, PL1V)</span><br><span>@@ -236,7 +236,7 @@</span><br><span>             Store (CTDN, PL1V)</span><br><span> </span><br><span>               /* Set PL2 */</span><br><span style="color: hsl(0, 100%, 40%);">-           Store (CPL2 (CTDN), PL2V)</span><br><span style="color: hsl(120, 100%, 40%);">+             Store (CPL2 (), PL2V)</span><br><span> </span><br><span>            /* Set PPC limit and notify OS */</span><br><span>            Store (PSSS (TARN), PPCM)</span><br><span>diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl</span><br><span>index e6aad21..0fc6c66 100644</span><br><span>--- a/src/soc/intel/broadwell/acpi/ctdp.asl</span><br><span>+++ b/src/soc/intel/broadwell/acpi/ctdp.asl</span><br><span>@@ -92,7 +92,7 @@</span><br><span>       }</span><br><span> </span><br><span>        /* Calculate PL2 based on chip type */</span><br><span style="color: hsl(0, 100%, 40%);">-  Method (CPL2, 1, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+       Method (CPL2, 0, NotSerialized)</span><br><span>      {</span><br><span>            /* Haswell ULT PL2 = 25W */</span><br><span>          /* FIXME: update for broadwell */</span><br><span>@@ -123,7 +123,7 @@</span><br><span>              PPCN ()</span><br><span> </span><br><span>          /* Set PL2 */</span><br><span style="color: hsl(0, 100%, 40%);">-           Store (CPL2 (CTDD), PL2V)</span><br><span style="color: hsl(120, 100%, 40%);">+             Store (CPL2 (), PL2V)</span><br><span> </span><br><span>            /* Set PL1 */</span><br><span>                Store (CTDD, PL1V)</span><br><span>@@ -152,7 +152,7 @@</span><br><span>             Store (CTDN, PL1V)</span><br><span> </span><br><span>               /* Set PL2 */</span><br><span style="color: hsl(0, 100%, 40%);">-           Store (CPL2 (CTDN), PL2V)</span><br><span style="color: hsl(120, 100%, 40%);">+             Store (CPL2 (), PL2V)</span><br><span> </span><br><span>            /* Set PPC limit and notify OS */</span><br><span>            Store (PSSS (TARN), PPCM)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26149">change 26149</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26149"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7fb96fc7f22a387d796752dcfce4639293c45e5e </div>
<div style="display:none"> Gerrit-Change-Number: 26149 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>