<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26175">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Support ACPI USB code generation<br><br>To support generating USB devices in ACPI the platform needs to<br>know how to determine a device name for each USB port, and for any<br>root hubs that may be present.<br><br>The AMD Stoney Ridge platform has separate controllers for USB 2.0<br>and USB 3.0. The USB 2.0 ports are connected through a hub to an<br>EHCI controller while the USB 3.0 ports are directly connected to<br>the xHCI controller.<br><br>This topology is described in ACPI and the port names are exposed<br>by the soc_acpi_name() function.<br><br>The USB controllers are configured to scan for static USB devices<br>in the devicetree and use the soc_acpi_name() function to identify<br>them.<br><br>Change-Id: I2bb677f84a49d2531929985dba319455b88e1686<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>---<br>M src/soc/amd/stoneyridge/acpi/usb.asl<br>M src/soc/amd/stoneyridge/chip.c<br>M src/soc/amd/stoneyridge/include/soc/acpi.h<br>M src/soc/amd/stoneyridge/usb.c<br>4 files changed, 52 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/26175/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl</span><br><span>index 3fd76b2..6c6ff9c 100644</span><br><span>--- a/src/soc/amd/stoneyridge/acpi/usb.asl</span><br><span>+++ b/src/soc/amd/stoneyridge/acpi/usb.asl</span><br><span>@@ -17,10 +17,24 @@</span><br><span> /* 0:12.0 - EHCI */</span><br><span> Device(EHC0) {</span><br><span> Name(_ADR, 0x00120000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (RHUB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, Zero)</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS01) { Name (_ADR, 1) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS02) { Name (_ADR, 2) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS03) { Name (_ADR, 3) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS04) { Name (_ADR, 4) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS05) { Name (_ADR, 5) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS06) { Name (_ADR, 6) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS07) { Name (_ADR, 7) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (HS08) { Name (_ADR, 8) }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> } /* end EHC0 */</span><br><span> </span><br><span> </span><br><span> /* 0:10.0 - XHCI 0*/</span><br><span> Device(XHC0) {</span><br><span> Name(_ADR, 0x00100000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (SS01) { Name (_ADR, 1) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (SS02) { Name (_ADR, 2) }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (SS03) { Name (_ADR, 3) }</span><br><span> } /* end XHC0 */</span><br><span>diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c</span><br><span>index f5efcfd..589724b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/chip.c</span><br><span>+++ b/src/soc/amd/stoneyridge/chip.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <device/pci.h></span><br><span> #include <drivers/i2c/designware/dw_i2c.h></span><br><span> #include <romstage_handoff.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/acpi.h></span><br><span> #include <soc/cpu.h></span><br><span> #include <soc/northbridge.h></span><br><span> #include <soc/pci_devs.h></span><br><span>@@ -42,10 +43,41 @@</span><br><span> .acpi_fill_ssdt_generator = generate_cpu_entries,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const char *soc_acpi_name(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+const char *soc_acpi_name(const struct device *dev)</span><br><span> {</span><br><span> if (dev->path.type == DEVICE_PATH_DOMAIN)</span><br><span> return "PCI0";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.type == DEVICE_PATH_USB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (dev->path.usb.port_type) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Root Hub */</span><br><span style="color: hsl(120, 100%, 40%);">+ return "RHUB";</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB2 ports */</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (dev->path.usb.port_id) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0: return "HS01";</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1: return "HS02";</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2: return "HS03";</span><br><span style="color: hsl(120, 100%, 40%);">+ case 3: return "HS04";</span><br><span style="color: hsl(120, 100%, 40%);">+ case 4: return "HS05";</span><br><span style="color: hsl(120, 100%, 40%);">+ case 5: return "HS06";</span><br><span style="color: hsl(120, 100%, 40%);">+ case 6: return "HS07";</span><br><span style="color: hsl(120, 100%, 40%);">+ case 7: return "HS08";</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 3:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB3 ports */</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (dev->path.usb.port_id) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0: return "SS01";</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1: return "SS02";</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2: return "SS03";</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> if (dev->path.type != DEVICE_PATH_PCI)</span><br><span> return NULL;</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h</span><br><span>index 3e58d9a..69ab599 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/acpi.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h</span><br><span>@@ -35,4 +35,6 @@</span><br><span> </span><br><span> void southbridge_inject_dsdt(device_t device);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+const char *soc_acpi_name(const struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif /* __SOC_STONEYRIDGE_ACPI_H__ */</span><br><span>diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c</span><br><span>index e6d608e..6007af1 100644</span><br><span>--- a/src/soc/amd/stoneyridge/usb.c</span><br><span>+++ b/src/soc/amd/stoneyridge/usb.c</span><br><span>@@ -21,6 +21,7 @@</span><br><span> #include <device/pci_ops.h></span><br><span> #include <device/pci_ehci.h></span><br><span> #include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/acpi.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/southbridge.h></span><br><span> </span><br><span>@@ -64,7 +65,8 @@</span><br><span> .set_resources = pci_dev_set_resources,</span><br><span> .enable_resources = pci_dev_enable_resources,</span><br><span> .init = set_usb_over_current,</span><br><span style="color: hsl(0, 100%, 40%);">- .scan_bus = NULL,</span><br><span style="color: hsl(120, 100%, 40%);">+ .scan_bus = scan_usb_bus,</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_name = soc_acpi_name,</span><br><span> .ops_pci = &lops_pci,</span><br><span> };</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26175">change 26175</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2bb677f84a49d2531929985dba319455b88e1686 </div>
<div style="display:none"> Gerrit-Change-Number: 26175 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>