<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26147">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Add early MTRR setup for new callouts<br><br>Enable the two ranges to be used for the new callouts, AgesaHeapRebase<br>and AgesaGetHeapBaseInDram.<br><br>T=Boot grunt w/experimental blob, try different addresses<br>BUG=b:74518368<br><br>Change-Id: Ic7716794dc7d75f849e6e062865d6efbeb4292df<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>M src/soc/amd/stoneyridge/include/soc/cpu.h<br>2 files changed, 25 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/26147/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>index 6ee2095..5daa1ea 100644</span><br><span>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>@@ -32,7 +32,14 @@</span><br><span> #include <timestamp.h></span><br><span> #include <halt.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Set the MMIO Configuration Base Address and Bus Range. */</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000</span><br><span style="color: hsl(120, 100%, 40%);">+#error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000</span><br><span style="color: hsl(120, 100%, 40%);">+#error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */</span><br><span> static void amd_initmmio(void)</span><br><span> {</span><br><span> msr_t mmconf;</span><br><span>@@ -47,9 +54,23 @@</span><br><span> /*</span><br><span> * todo: AGESA currently writes variable MTRRs. Once that is</span><br><span> * corrected, un-hardcode this MTRR.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Be careful not to use get_free_var_mtrr/set_var_mtrr pairs</span><br><span style="color: hsl(120, 100%, 40%);">+ * where all cores execute the path. Both cores within a compute</span><br><span style="color: hsl(120, 100%, 40%);">+ * unit share MTRRs. Programming core0 has the appearance of</span><br><span style="color: hsl(120, 100%, 40%);">+ * modifying core1 too. Using the pair again will create</span><br><span style="color: hsl(120, 100%, 40%);">+ * duplicate copies.</span><br><span> */</span><br><span> mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH;</span><br><span> set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP;</span><br><span style="color: hsl(120, 100%, 40%);">+ set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM;</span><br><span style="color: hsl(120, 100%, 40%);">+ set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK);</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h</span><br><span>index bf8ed49..3d230c3 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/cpu.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/cpu.h</span><br><span>@@ -25,7 +25,9 @@</span><br><span> *</span><br><span> * todo: Revisit this once AGESA no longer programs MTRRs.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SOC_EARLY_VMTRR_FLASH 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_EARLY_VMTRR_FLASH 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_EARLY_VMTRR_CAR_HEAP 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_EARLY_VMTRR_TEMPRAM 3</span><br><span> </span><br><span> void stoney_init_cpus(struct device *dev);</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26147">change 26147</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic7716794dc7d75f849e6e062865d6efbeb4292df </div>
<div style="display:none"> Gerrit-Change-Number: 26147 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Marshall Dawson <marshall.dawson@scarletltd.com> </div>