<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26140">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Support PCH UART 0 and 1 for console<br><br>The current PCH UART support for console is limited to UART2.<br><br>This change adds support for specifying UART0 or UART1 to be<br>used instead by changing CONFIG_UART_FOR_CONSOLE in the board<br>level Kconfig. The default is still 2.<br><br>This is tested with a board that uses UART0 for debug output.<br><br>Change-Id: I91323ed3298f9b2558764aa4b54173833c021a7b<br>Signed-off-by: Duncan Laurie <dlaurie@chromium.org><br>---<br>M src/soc/intel/skylake/uart.c<br>1 file changed, 27 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/26140/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c</span><br><span>index 6f3c21e..1b4e96e 100644</span><br><span>--- a/src/soc/intel/skylake/uart.c</span><br><span>+++ b/src/soc/intel/skylake/uart.c</span><br><span>@@ -31,10 +31,20 @@</span><br><span> #define PCR_SERIAL_IO_GPPRVRW7 0x618</span><br><span> #define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2 pad configuration. Support RXD and TXD for now. */</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pad_config uart2_pads[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART pad configuration. Support RXD and TXD for now. */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config uart_pads[][2] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> };</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)</span><br><span>@@ -50,9 +60,9 @@</span><br><span> {</span><br><span> uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- uart_common_init(PCH_DEV_UART2, base);</span><br><span style="color: hsl(120, 100%, 40%);">+ uart_common_init(pch_uart_get_debug_controller(), base);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Put UART2 in byte access mode for 16550 compatibility */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Put UART in byte access mode for 16550 compatibility */</span><br><span> if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {</span><br><span> pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,</span><br><span> PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));</span><br><span>@@ -64,7 +74,8 @@</span><br><span> lpss_clk_read(base);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure_pads(uart_pads[CONFIG_UART_FOR_CONSOLE],</span><br><span style="color: hsl(120, 100%, 40%);">+ ARRAY_SIZE(uart_pads[CONFIG_UART_FOR_CONSOLE]));</span><br><span> }</span><br><span> </span><br><span> #if !ENV_SMM</span><br><span>@@ -96,5 +107,13 @@</span><br><span> </span><br><span> device_t pch_uart_get_debug_controller(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return PCH_DEV_UART2;</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (CONFIG_UART_FOR_CONSOLE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0:</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_DEV_UART0;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_DEV_UART1;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2:</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCH_DEV_UART2;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26140">change 26140</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I91323ed3298f9b2558764aa4b54173833c021a7b </div>
<div style="display:none"> Gerrit-Change-Number: 26140 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>