<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26050">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]superio/nuvoton/npcd378: Add PSU fan control<br><br>Implement method to access HWM space and set the PSU fan using a new<br>CMOS option psu_fan_lvl. Add the CMOS option to all board that use<br>NPCD378. In case no CMOS is set use the default fan level 3.<br><br>Change-Id: I56ce7ad1df88638589a577b8a09d5d775557887b<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/mainboard/hp/compaq_8200_elite_sff/cmos.default<br>M src/mainboard/hp/compaq_8200_elite_sff/cmos.layout<br>M src/superio/nuvoton/npcd378/npcd378.h<br>M src/superio/nuvoton/npcd378/superio.c<br>4 files changed, 85 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/26050/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default</span><br><span>index d00ae5e..306760c 100644</span><br><span>--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default</span><br><span>@@ -3,3 +3,4 @@</span><br><span> power_on_after_fail=Enable</span><br><span> nmi=Enable</span><br><span> sata_mode=AHCI</span><br><span style="color: hsl(120, 100%, 40%);">+psu_fan_lvl=3</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout</span><br><span>index 3ead211..830d286 100644</span><br><span>--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout</span><br><span>@@ -51,7 +51,9 @@</span><br><span> # coreboot config options: console</span><br><span> #392 3 r 0 unused</span><br><span> 395 4 e 6 debug_level</span><br><span style="color: hsl(0, 100%, 40%);">-#399 9 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+400 3 h 0 psu_fan_lvl</span><br><span style="color: hsl(120, 100%, 40%);">+#403 5 r 0 unused</span><br><span> </span><br><span> # coreboot config options: southbridge</span><br><span> 408 1 e 1 nmi</span><br><span>diff --git a/src/superio/nuvoton/npcd378/npcd378.h b/src/superio/nuvoton/npcd378/npcd378.h</span><br><span>index 732dd00..902608c 100644</span><br><span>--- a/src/superio/nuvoton/npcd378/npcd378.h</span><br><span>+++ b/src/superio/nuvoton/npcd378/npcd378.h</span><br><span>@@ -17,6 +17,31 @@</span><br><span> #ifndef SUPERIO_NUVOTON_NPCD378_H</span><br><span> #define SUPERIO_NUVOTON_NPCD378_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* HWM at LDN8 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_HWM_PSU_FAN_MIN 0x17</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_HWM_PSU_FAN_MAX 0xf8</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_HWM_PSU_FAN_PWM_CTRL 0x198</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Read HWM register at specific page and offset.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param iobase IOBASE address of LDN8</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param reg MSB is page, LSB sets the offset in selected page</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * @return Byte read from HWM</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+uint8_t npcd378_hwm_read(const uint16_t iobase, const uint16_t reg);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Write to HWM register at specific page and offset.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param iobase IOBASE address of LDN8</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param reg MSB is page, LSB sets the offset in selected page</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param val The value to write to HWM register</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void npcd378_hwm_write(const uint16_t iobase, const uint16_t reg,</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint8_t val);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Logical Device Numbers (LDN). */</span><br><span> /* Default Nuvoton hardware: */</span><br><span> #define NPCD378_FDC 0x00 /* Floppy */</span><br><span>diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c</span><br><span>index a05d199..1f5ac72 100644</span><br><span>--- a/src/superio/nuvoton/npcd378/superio.c</span><br><span>+++ b/src/superio/nuvoton/npcd378/superio.c</span><br><span>@@ -18,24 +18,79 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pnp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <option.h></span><br><span> #include <pc80/keyboard.h></span><br><span> #include <stdlib.h></span><br><span> #include <superio/conf_mode.h></span><br><span> </span><br><span> #include "npcd378.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+uint8_t npcd378_hwm_read(const uint16_t iobase, const uint16_t reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ outb((reg >> 8) & 0xf, iobase + 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t reg8 = inb(iobase + (reg & 0xff));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (reg8 == 0xff)</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = inb(iobase + (reg & 0xff));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0, iobase + 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+ return reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void npcd378_hwm_write(const uint16_t iobase, const uint16_t reg,</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint8_t val)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ outb((reg >> 8) & 0xf, iobase + 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(val, iobase + (reg & 0xff));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0, iobase + 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint16_t npcd378_get_iobase(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct resource *res;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (res = dev->resource_list; res; res = res->next)</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((res->flags & IORESOURCE_IO) && (res->index == 0x60))</span><br><span style="color: hsl(120, 100%, 40%);">+ return res->base;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void npcd378_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t hwm_iobase;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pwm, fan_lvl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> if (!dev->enabled)</span><br><span> return;</span><br><span> </span><br><span> switch (dev->path.pnp.device) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* TODO: Might potentially need code for HWM or FDC etc. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO: Might potentially need code for FDC etc. */</span><br><span> case NPCD378_KBC:</span><br><span> pc_keyboard_init(PROBE_AUX_DEVICE);</span><br><span> break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case NPCD378_HWM:</span><br><span style="color: hsl(120, 100%, 40%);">+ hwm_iobase = npcd378_get_iobase(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!hwm_iobase) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "NPCD378: LDN%u IOBASE not set.\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ NPCD378_HWM);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!get_option(&fan_lvl, "psu_fan_lvl") || fan_lvl > 7)</span><br><span style="color: hsl(120, 100%, 40%);">+ fan_lvl = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pwm = NPCD378_HWM_PSU_FAN_MIN +</span><br><span style="color: hsl(120, 100%, 40%);">+ (NPCD378_HWM_PSU_FAN_MAX - NPCD378_HWM_PSU_FAN_MIN) *</span><br><span style="color: hsl(120, 100%, 40%);">+ fan_lvl / 7;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set PSU fan PWM lvl */</span><br><span style="color: hsl(120, 100%, 40%);">+ npcd378_hwm_write(hwm_iobase, NPCD378_HWM_PSU_FAN_PWM_CTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ pwm);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "NPCD378: PSU fan PWM 0x%02x\n", pwm);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span> }</span><br><span> }</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26050">change 26050</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I56ce7ad1df88638589a577b8a09d5d775557887b </div>
<div style="display:none"> Gerrit-Change-Number: 26050 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>