<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26055">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">{mb,nb,soc}: Remove references to pci_bus_default_ops()<br><br>pci_bus_default_ops() is the default anyway.<br><br>Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6<br>Signed-off-by: Nico Huber <nico.huber@secunet.com><br>---<br>M Documentation/Intel/SoC/soc.html<br>M src/mainboard/emulation/qemu-i440fx/northbridge.c<br>M src/northbridge/amd/agesa/family15tn/northbridge.c<br>M src/northbridge/amd/agesa/family16kb/northbridge.c<br>M src/northbridge/amd/amdfam10/northbridge.c<br>M src/northbridge/amd/amdk8/northbridge.c<br>M src/northbridge/amd/lx/northbridge.c<br>M src/northbridge/amd/pi/00630F01/northbridge.c<br>M src/northbridge/amd/pi/00660F01/northbridge.c<br>M src/northbridge/amd/pi/00730F01/northbridge.c<br>M src/northbridge/intel/e7505/northbridge.c<br>M src/northbridge/intel/fsp_rangeley/northbridge.c<br>M src/northbridge/intel/fsp_sandybridge/northbridge.c<br>M src/northbridge/intel/gm45/northbridge.c<br>M src/northbridge/intel/haswell/northbridge.c<br>M src/northbridge/intel/i440bx/northbridge.c<br>M src/northbridge/intel/i945/northbridge.c<br>M src/northbridge/intel/nehalem/northbridge.c<br>M src/northbridge/intel/pineview/northbridge.c<br>M src/northbridge/intel/sandybridge/northbridge.c<br>M src/northbridge/intel/x4x/northbridge.c<br>M src/northbridge/via/cn700/northbridge.c<br>M src/northbridge/via/cx700/northbridge.c<br>M src/northbridge/via/vx800/northbridge.c<br>M src/northbridge/via/vx900/northbridge.c<br>M src/soc/amd/stoneyridge/chip.c<br>M src/soc/intel/apollolake/chip.c<br>M src/soc/intel/baytrail/chip.c<br>M src/soc/intel/braswell/chip.c<br>M src/soc/intel/broadwell/chip.c<br>M src/soc/intel/cannonlake/chip.c<br>M src/soc/intel/denverton_ns/chip.c<br>M src/soc/intel/fsp_baytrail/chip.c<br>M src/soc/intel/fsp_broadwell_de/chip.c<br>M src/soc/intel/quark/chip.c<br>M src/soc/intel/skylake/chip.c<br>M src/soc/intel/skylake/chip_fsp20.c<br>37 files changed, 0 insertions(+), 37 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/26055/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html</span><br><span>index d91166f..b4804de 100644</span><br><span>--- a/Documentation/Intel/SoC/soc.html</span><br><span>+++ b/Documentation/Intel/SoC/soc.html</span><br><span>@@ -456,7 +456,6 @@</span><br><span> .read_resources = pci_domain_read_resources,</span><br><span> .set_resources = pci_domain_set_resources,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </code></pre></span><br><span> </li></span><br><span>diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c</span><br><span>index 18dcae3..9305ffb 100644</span><br><span>--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c</span><br><span>+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c</span><br><span>@@ -230,7 +230,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)</span><br><span> .get_smbios_data = qemu_get_smbios_data,</span><br><span> #endif</span><br><span>diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c</span><br><span>index 6face48..f47d312 100644</span><br><span>--- a/src/northbridge/amd/agesa/family15tn/northbridge.c</span><br><span>+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c</span><br><span>@@ -784,7 +784,6 @@</span><br><span> .set_resources = domain_set_resources,</span><br><span> .init = DEVICE_NOOP,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void sysconf_init(device_t dev) // first node</span><br><span>diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c</span><br><span>index 98ed2b8..f667f6f 100644</span><br><span>--- a/src/northbridge/amd/agesa/family16kb/northbridge.c</span><br><span>+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c</span><br><span>@@ -800,7 +800,6 @@</span><br><span> .set_resources = domain_set_resources,</span><br><span> .init = DEVICE_NOOP,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void sysconf_init(device_t dev) // first node</span><br><span>diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c</span><br><span>index 61c4465..f50c2ee 100644</span><br><span>--- a/src/northbridge/amd/amdfam10/northbridge.c</span><br><span>+++ b/src/northbridge/amd/amdfam10/northbridge.c</span><br><span>@@ -1326,7 +1326,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = amdfam10_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span> .acpi_name = amdfam10_domain_acpi_name,</span><br><span> #endif</span><br><span>diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c</span><br><span>index 2a92ca2..0a16db4 100644</span><br><span>--- a/src/northbridge/amd/amdk8/northbridge.c</span><br><span>+++ b/src/northbridge/amd/amdk8/northbridge.c</span><br><span>@@ -1053,7 +1053,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = amdk8_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void add_more_links(device_t dev, unsigned total_links)</span><br><span>diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c</span><br><span>index 93ec350..543b691 100644</span><br><span>--- a/src/northbridge/amd/lx/northbridge.c</span><br><span>+++ b/src/northbridge/amd/lx/northbridge.c</span><br><span>@@ -391,7 +391,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span> .enable = pci_domain_enable,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void cpu_bus_init(device_t dev)</span><br><span>diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c</span><br><span>index 74f190c..f542495 100644</span><br><span>--- a/src/northbridge/amd/pi/00630F01/northbridge.c</span><br><span>+++ b/src/northbridge/amd/pi/00630F01/northbridge.c</span><br><span>@@ -800,7 +800,6 @@</span><br><span> .enable_resources = domain_enable_resources,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void sysconf_init(device_t dev) // first node</span><br><span>diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c</span><br><span>index c949a9a..aa2aa1c 100644</span><br><span>--- a/src/northbridge/amd/pi/00660F01/northbridge.c</span><br><span>+++ b/src/northbridge/amd/pi/00660F01/northbridge.c</span><br><span>@@ -802,7 +802,6 @@</span><br><span> .enable_resources = domain_enable_resources,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void sysconf_init(device_t dev) // first node</span><br><span>diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c</span><br><span>index 8e8e228..6e652c0e 100644</span><br><span>--- a/src/northbridge/amd/pi/00730F01/northbridge.c</span><br><span>+++ b/src/northbridge/amd/pi/00730F01/northbridge.c</span><br><span>@@ -824,7 +824,6 @@</span><br><span> .enable_resources = domain_enable_resources,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> .acpi_name = domain_acpi_name,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c</span><br><span>index f6e14d6..23012d6 100644</span><br><span>--- a/src/northbridge/intel/e7505/northbridge.c</span><br><span>+++ b/src/northbridge/intel/e7505/northbridge.c</span><br><span>@@ -114,7 +114,6 @@</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span> .ops_pci = &intel_pci_ops,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void cpu_bus_init(device_t dev)</span><br><span>diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c</span><br><span>index 22e6cee..af652ee 100644</span><br><span>--- a/src/northbridge/intel/fsp_rangeley/northbridge.c</span><br><span>+++ b/src/northbridge/intel/fsp_rangeley/northbridge.c</span><br><span>@@ -203,7 +203,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static struct device_operations mc_ops = {</span><br><span>diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c</span><br><span>index a565b8d..2dfe44d 100644</span><br><span>--- a/src/northbridge/intel/fsp_sandybridge/northbridge.c</span><br><span>+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c</span><br><span>@@ -233,7 +233,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void mc_read_resources(device_t dev)</span><br><span>diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c</span><br><span>index f682da7..4c42513 100644</span><br><span>--- a/src/northbridge/intel/gm45/northbridge.c</span><br><span>+++ b/src/northbridge/intel/gm45/northbridge.c</span><br><span>@@ -197,7 +197,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = mch_domain_init,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> .write_acpi_tables = northbridge_write_acpi_tables,</span><br><span> .acpi_fill_ssdt_generator = generate_cpu_entries,</span><br><span> };</span><br><span>diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c</span><br><span>index bbf1604..095c684 100644</span><br><span>--- a/src/northbridge/intel/haswell/northbridge.c</span><br><span>+++ b/src/northbridge/intel/haswell/northbridge.c</span><br><span>@@ -84,7 +84,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> .write_acpi_tables = northbridge_write_acpi_tables,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c</span><br><span>index 1245be6..b993817 100644</span><br><span>--- a/src/northbridge/intel/i440bx/northbridge.c</span><br><span>+++ b/src/northbridge/intel/i440bx/northbridge.c</span><br><span>@@ -79,7 +79,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void cpu_bus_init(struct device *dev)</span><br><span>diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c</span><br><span>index 794c61e..eb8e321 100644</span><br><span>--- a/src/northbridge/intel/i945/northbridge.c</span><br><span>+++ b/src/northbridge/intel/i945/northbridge.c</span><br><span>@@ -146,7 +146,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void mc_read_resources(struct device *dev)</span><br><span>diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c</span><br><span>index 37662d5..fa5d595 100644</span><br><span>--- a/src/northbridge/intel/nehalem/northbridge.c</span><br><span>+++ b/src/northbridge/intel/nehalem/northbridge.c</span><br><span>@@ -98,7 +98,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void mc_read_resources(struct device *dev)</span><br><span>diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c</span><br><span>index 61b9edb..93c7558 100644</span><br><span>--- a/src/northbridge/intel/pineview/northbridge.c</span><br><span>+++ b/src/northbridge/intel/pineview/northbridge.c</span><br><span>@@ -152,7 +152,6 @@</span><br><span> .set_resources = mch_domain_set_resources,</span><br><span> .init = mch_domain_init,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> .acpi_fill_ssdt_generator = generate_cpu_entries,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c</span><br><span>index 322e4b8..eb8ce26 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/northbridge.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/northbridge.c</span><br><span>@@ -268,7 +268,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> .write_acpi_tables = northbridge_write_acpi_tables,</span><br><span> .acpi_name = northbridge_acpi_name,</span><br><span> };</span><br><span>diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c</span><br><span>index e51c587..3e50229 100644</span><br><span>--- a/src/northbridge/intel/x4x/northbridge.c</span><br><span>+++ b/src/northbridge/intel/x4x/northbridge.c</span><br><span>@@ -161,7 +161,6 @@</span><br><span> .set_resources = mch_domain_set_resources,</span><br><span> .init = mch_domain_init,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> .write_acpi_tables = northbridge_write_acpi_tables,</span><br><span> .acpi_fill_ssdt_generator = generate_cpu_entries,</span><br><span> };</span><br><span>diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c</span><br><span>index 2121162..f745a0e 100644</span><br><span>--- a/src/northbridge/via/cn700/northbridge.c</span><br><span>+++ b/src/northbridge/via/cn700/northbridge.c</span><br><span>@@ -149,7 +149,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void cpu_bus_init(device_t dev)</span><br><span>diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c</span><br><span>index 19bdf11..51e7861 100644</span><br><span>--- a/src/northbridge/via/cx700/northbridge.c</span><br><span>+++ b/src/northbridge/via/cx700/northbridge.c</span><br><span>@@ -104,7 +104,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> .write_acpi_tables = acpi_write_hpet,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c</span><br><span>index e6ec3b5..609abf8 100644</span><br><span>--- a/src/northbridge/via/vx800/northbridge.c</span><br><span>+++ b/src/northbridge/via/vx800/northbridge.c</span><br><span>@@ -122,7 +122,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void cpu_bus_init(device_t dev)</span><br><span>diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c</span><br><span>index 774f744..bf6cb66 100644</span><br><span>--- a/src/northbridge/via/vx900/northbridge.c</span><br><span>+++ b/src/northbridge/via/vx900/northbridge.c</span><br><span>@@ -310,7 +310,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void cpu_bus_init(device_t dev)</span><br><span>diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c</span><br><span>index f5efcfd..08eecb9 100644</span><br><span>--- a/src/soc/amd/stoneyridge/chip.c</span><br><span>+++ b/src/soc/amd/stoneyridge/chip.c</span><br><span>@@ -72,7 +72,6 @@</span><br><span> .set_resources = domain_set_resources,</span><br><span> .enable_resources = domain_enable_resources,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> .acpi_name = soc_acpi_name,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c</span><br><span>index e4084fe..fee9841 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.c</span><br><span>+++ b/src/soc/intel/apollolake/chip.c</span><br><span>@@ -132,7 +132,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> .acpi_name = &soc_acpi_name,</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c</span><br><span>index 5c6a891..dab2cd1 100644</span><br><span>--- a/src/soc/intel/baytrail/chip.c</span><br><span>+++ b/src/soc/intel/baytrail/chip.c</span><br><span>@@ -33,7 +33,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static struct device_operations cpu_bus_ops = {</span><br><span>diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c</span><br><span>index 3da5763..49e5ce6 100644</span><br><span>--- a/src/soc/intel/braswell/chip.c</span><br><span>+++ b/src/soc/intel/braswell/chip.c</span><br><span>@@ -36,7 +36,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void cpu_bus_noop(device_t dev) { }</span><br><span>diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c</span><br><span>index c282c6b..ae3248a 100644</span><br><span>--- a/src/soc/intel/broadwell/chip.c</span><br><span>+++ b/src/soc/intel/broadwell/chip.c</span><br><span>@@ -30,7 +30,6 @@</span><br><span> .read_resources = &pci_domain_read_resources,</span><br><span> .set_resources = &pci_domain_set_resources,</span><br><span> .scan_bus = &pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = &pci_bus_default_ops,</span><br><span> #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span> .write_acpi_tables = &northbridge_write_acpi_tables,</span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index 49b98ee..b64d804 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -148,7 +148,6 @@</span><br><span> .read_resources = &pci_domain_read_resources,</span><br><span> .set_resources = &pci_domain_set_resources,</span><br><span> .scan_bus = &pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = &pci_bus_default_ops,</span><br><span> #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span> .acpi_name = &soc_acpi_name,</span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c</span><br><span>index a43504c..6600ba2 100644</span><br><span>--- a/src/soc/intel/denverton_ns/chip.c</span><br><span>+++ b/src/soc/intel/denverton_ns/chip.c</span><br><span>@@ -42,7 +42,6 @@</span><br><span> .read_resources = &pci_domain_read_resources,</span><br><span> .set_resources = &pci_domain_set_resources,</span><br><span> .scan_bus = &pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = &pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static struct device_operations cpu_bus_ops = {</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c</span><br><span>index 6bdb7b4..814417a 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/chip.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/chip.c</span><br><span>@@ -32,7 +32,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static struct device_operations cpu_bus_ops = {</span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c</span><br><span>index 118fb99..d033374 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/chip.c</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/chip.c</span><br><span>@@ -45,7 +45,6 @@</span><br><span> .enable_resources = NULL,</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span> .acpi_name = domain_acpi_name</span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c</span><br><span>index 5e80463..91ab8f5 100644</span><br><span>--- a/src/soc/intel/quark/chip.c</span><br><span>+++ b/src/soc/intel/quark/chip.c</span><br><span>@@ -130,7 +130,6 @@</span><br><span> .read_resources = pci_domain_read_resources,</span><br><span> .set_resources = pci_domain_set_resources,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span> static void chip_enable_dev(device_t dev)</span><br><span>diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c</span><br><span>index 0c1dfa6..bb2ecaa 100644</span><br><span>--- a/src/soc/intel/skylake/chip.c</span><br><span>+++ b/src/soc/intel/skylake/chip.c</span><br><span>@@ -48,7 +48,6 @@</span><br><span> .read_resources = &pci_domain_read_resources,</span><br><span> .set_resources = &pci_domain_set_resources,</span><br><span> .scan_bus = &pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = &pci_bus_default_ops,</span><br><span> #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span> .acpi_name = &soc_acpi_name,</span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>index 6e91816..0d0821b 100644</span><br><span>--- a/src/soc/intel/skylake/chip_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>@@ -59,7 +59,6 @@</span><br><span> .read_resources = &pci_domain_read_resources,</span><br><span> .set_resources = &pci_domain_set_resources,</span><br><span> .scan_bus = &pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci_bus = &pci_bus_default_ops,</span><br><span> #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span> .write_acpi_tables = &northbridge_write_acpi_tables,</span><br><span> .acpi_name = &soc_acpi_name,</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26055">change 26055</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26055"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 </div>
<div style="display:none"> Gerrit-Change-Number: 26055 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>