<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26003">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/device/pciexp_device.c: Get rid of device_t<br><br>Use of `device_t` has been abandoned in ramstage.<br><br>Change-Id: I82b73e1698d8d44e32ad9f21e575a7fce35baa1c<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/device/pciexp_device.c<br>1 file changed, 22 insertions(+), 22 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/26003/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c</span><br><span>index 502494d..8cd39e4 100644</span><br><span>--- a/src/device/pciexp_device.c</span><br><span>+++ b/src/device/pciexp_device.c</span><br><span>@@ -22,7 +22,7 @@</span><br><span> #include <device/pci_ops.h></span><br><span> #include <device/pciexp.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap)</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap)</span><br><span> {</span><br><span> unsigned int this_cap_offset, next_cap_offset;</span><br><span> unsigned int this_cap, cafe;</span><br><span>@@ -49,7 +49,7 @@</span><br><span> * Re-train a PCIe link</span><br><span> */</span><br><span> #define PCIE_TRAIN_RETRY 10000</span><br><span style="color: hsl(0, 100%, 40%);">-static int pciexp_retrain_link(device_t dev, unsigned cap)</span><br><span style="color: hsl(120, 100%, 40%);">+static int pciexp_retrain_link(struct device *dev, unsigned cap)</span><br><span> {</span><br><span> unsigned int try;</span><br><span> u16 lnk;</span><br><span>@@ -94,8 +94,8 @@</span><br><span> * and enable Common Clock Configuration if possible. If CCC is</span><br><span> * enabled the link must be retrained.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void pciexp_enable_common_clock(device_t root, unsigned root_cap,</span><br><span style="color: hsl(0, 100%, 40%);">- device_t endp, unsigned endp_cap)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pciexp_enable_common_clock(struct device *root, unsigned root_cap,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *endp, unsigned endp_cap)</span><br><span> {</span><br><span> u16 root_scc, endp_scc, lnkctl;</span><br><span> </span><br><span>@@ -126,7 +126,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pciexp_enable_clock_power_pm(struct device *endp, unsigned endp_cap)</span><br><span> {</span><br><span> /* check if per port clk req is supported in device */</span><br><span> u32 endp_ca;</span><br><span>@@ -141,7 +141,7 @@</span><br><span> pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pciexp_config_max_latency(device_t root, device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pciexp_config_max_latency(struct device *root, struct device *dev)</span><br><span> {</span><br><span> unsigned int cap;</span><br><span> cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID);</span><br><span>@@ -150,7 +150,7 @@</span><br><span> root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static bool pciexp_is_ltr_supported(device_t dev, unsigned int cap)</span><br><span style="color: hsl(120, 100%, 40%);">+static bool pciexp_is_ltr_supported(struct device *dev, unsigned int cap)</span><br><span> {</span><br><span> unsigned int val;</span><br><span> </span><br><span>@@ -162,7 +162,7 @@</span><br><span> return false;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pciexp_configure_ltr(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pciexp_configure_ltr(struct device *dev)</span><br><span> {</span><br><span> unsigned int cap;</span><br><span> </span><br><span>@@ -187,10 +187,10 @@</span><br><span> pciexp_config_max_latency(dev->bus->dev, dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pciexp_enable_ltr(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pciexp_enable_ltr(struct device *dev)</span><br><span> {</span><br><span> struct bus *bus;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t child;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *child;</span><br><span> </span><br><span> for (bus = dev->link_list ; bus ; bus = bus->next) {</span><br><span> for (child = bus->children; child; child = child->sibling) {</span><br><span>@@ -201,7 +201,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap,</span><br><span style="color: hsl(120, 100%, 40%);">+static unsigned char pciexp_L1_substate_cal(struct device *dev, unsigned int endp_cap,</span><br><span> unsigned int *data)</span><br><span> {</span><br><span> unsigned char mult[4] = {2, 10, 100, 0};</span><br><span>@@ -236,10 +236,10 @@</span><br><span> return 1;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pciexp_L1_substate_commit(device_t root, device_t dev,</span><br><span style="color: hsl(120, 100%, 40%);">+static void pciexp_L1_substate_commit(struct device *root, struct device *dev,</span><br><span> unsigned int root_cap, unsigned int end_cap)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev_t;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev_t;</span><br><span> unsigned char L1_ss_ok;</span><br><span> unsigned int rp_L1_support = pci_read_config32(root, root_cap + 4);</span><br><span> unsigned int L1SubStateSupport;</span><br><span>@@ -305,7 +305,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pciexp_config_L1_sub_state(device_t root, device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pciexp_config_L1_sub_state(struct device *root, struct device *dev)</span><br><span> {</span><br><span> unsigned int root_cap, end_cap;</span><br><span> </span><br><span>@@ -332,8 +332,8 @@</span><br><span> * by checking both root port and endpoint and returning</span><br><span> * the highest latency value.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static int pciexp_aspm_latency(device_t root, unsigned root_cap,</span><br><span style="color: hsl(0, 100%, 40%);">- device_t endp, unsigned endp_cap,</span><br><span style="color: hsl(120, 100%, 40%);">+static int pciexp_aspm_latency(struct device *root, unsigned root_cap,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *endp, unsigned endp_cap,</span><br><span> enum aspm_type type)</span><br><span> {</span><br><span> int root_lat = 0, endp_lat = 0;</span><br><span>@@ -368,8 +368,8 @@</span><br><span> /*</span><br><span> * Enable ASPM on PCIe root port and endpoint.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void pciexp_enable_aspm(device_t root, unsigned root_cap,</span><br><span style="color: hsl(0, 100%, 40%);">- device_t endp, unsigned endp_cap)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pciexp_enable_aspm(struct device *root, unsigned root_cap,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *endp, unsigned endp_cap)</span><br><span> {</span><br><span> const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" };</span><br><span> enum aspm_type apmc = PCIE_ASPM_NONE;</span><br><span>@@ -412,9 +412,9 @@</span><br><span> printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pciexp_tune_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pciexp_tune_dev(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t root = dev->bus->dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *root = dev->bus->dev;</span><br><span> unsigned int root_cap, cap;</span><br><span> </span><br><span> cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);</span><br><span>@@ -445,7 +445,7 @@</span><br><span> void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,</span><br><span> unsigned int max_devfn)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t child;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *child;</span><br><span> pci_scan_bus(bus, min_devfn, max_devfn);</span><br><span> </span><br><span> for (child = bus->children; child; child = child->sibling) {</span><br><span>@@ -457,7 +457,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void pciexp_scan_bridge(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void pciexp_scan_bridge(struct device *dev)</span><br><span> {</span><br><span> do_pci_scan_bridge(dev, pciexp_scan_bus);</span><br><span> pciexp_enable_ltr(dev);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26003">change 26003</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I82b73e1698d8d44e32ad9f21e575a7fce35baa1c </div>
<div style="display:none"> Gerrit-Change-Number: 26003 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>