<p>Nico Huber <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/25551">View Change</a></p><div style="white-space:pre-wrap">Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/sapphire/pureplatinumh61: Use custom SPI OPMENU<br><br>The SPI chip in this board needs a custom OPMENU, otherwise flashrom<br>fails halfway during the write.<br><br>From the default OPMENU, Block Erase (0xd8) has been replaced by AAI<br>write (0xad) and Fast Read (0x0b) by Write Disable (0x04).<br><br>Change-Id: Ie18ee4e32511482dab747c9ffeac60d3994df320<br>Signed-off-by: Nicola Corna <nicola@corna.info><br>Reviewed-on: https://review.coreboot.org/25551<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/mainboard/sapphire/pureplatinumh61/devicetree.cb<br>1 file changed, 2 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb</span><br><span>index 710004f..ed0d997 100644</span><br><span>--- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb</span><br><span>+++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb</span><br><span>@@ -59,6 +59,8 @@</span><br><span>                  register "pcie_port_coalesce" = "1"</span><br><span>                      register "sata_interface_speed_support" = "0x3"</span><br><span>                  register "sata_port_map" = "0x33"</span><br><span style="color: hsl(120, 100%, 40%);">+                 register "spi.opprefixes" = "{ 0x50, 0x06 }"</span><br><span style="color: hsl(120, 100%, 40%);">+                      register "spi.ops" = "{ { 0, 1, 0x01 }, { 1, 1, 0x02 }, { 1, 0, 0x03 }, { 0, 0, 0x05 }, { 1, 1, 0x20 }, { 0, 0, 0x9f }, { 0, 1, 0xad }, { 0, 1, 0x04 } }"</span><br><span>                        device pci 16.0 on # Management Engine Interface 1</span><br><span>                           subsystemid 0x174b 0x1007</span><br><span>                    end</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25551">change 25551</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25551"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: Ie18ee4e32511482dab747c9ffeac60d3994df320 </div>
<div style="display:none"> Gerrit-Change-Number: 25551 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Nicola Corna <nicola@corna.info> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>