<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25969">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: remove sb_set_readspeed function<br><br>The sb_set_readspeed() was touching the wrong register and<br>the read speed settings are handled by sb_set_spi100(). Nothing<br>was using the function, so remove it.<br><br>Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb<br>Signed-off-by: Marc Jones <marc.jones@scarletltd.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 0 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/25969/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 96826e3..0a23fca 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -379,7 +379,6 @@</span><br><span> void sb_pci_port80(void);</span><br><span> void sb_read_mode(u32 mode);</span><br><span> void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);</span><br><span style="color: hsl(0, 100%, 40%);">-void sb_set_readspeed(u16 norm, u16 fast);</span><br><span> void sb_tpm_decode(void);</span><br><span> void sb_tpm_decode_spi(void);</span><br><span> void lpc_wideio_512_window(uint16_t base);</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index a767e0c..eb8820f 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -442,15 +442,6 @@</span><br><span>                                     & ~SPI_RD4DW_EN_HOST);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void sb_set_readspeed(u16 norm, u16 fast)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-   uintptr_t base = sb_spibase();</span><br><span style="color: hsl(0, 100%, 40%);">-  write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1)</span><br><span style="color: hsl(0, 100%, 40%);">-                                   & ~SPI_CNTRL1_SPEED_MASK)</span><br><span style="color: hsl(0, 100%, 40%);">-                                   | (norm << SPI_NORM_SPEED_SH)</span><br><span style="color: hsl(0, 100%, 40%);">-                                     | (fast << SPI_FAST_SPEED_SH));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void sb_read_mode(u32 mode)</span><br><span> {</span><br><span>   uintptr_t base = sb_spibase();</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25969">change 25969</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25969"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb </div>
<div style="display:none"> Gerrit-Change-Number: 25969 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>