<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25921">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Documentation/Intel: Add MultiProcessorInit documentation<br><br>Add documentation for MP service PPI using EFI interface<br>on Intel 9th Gen Platforms.<br><br>Documented so far:<br>* Problem Statement<br>* New Design Proposal<br>* API interface<br>* Code Flow changes<br>* Benefits<br><br>BRANCH=none<br>BUG=b:74436746<br>TEST=none<br><br>Change-Id: I5b6096ef31d8a523c00cbad39ab9d4884e735fde<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>A Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png<br>A Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md<br>2 files changed, 74 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/25921/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png b/Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png</span><br><span>new file mode 100644</span><br><span>index 0000000..5836140</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png</span><br><span>Binary files differ</span><br><span>diff --git a/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md b/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md</span><br><span>new file mode 100644</span><br><span>index 0000000..6187631</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md</span><br><span>@@ -0,0 +1,74 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# Intel Common Code Block Publishing EFI_MP_SERVICES_PPI</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Introduction</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This documentation is intended to document the purpose for creating EFI service</span><br><span style="color: hsl(120, 100%, 40%);">+Interface inside Coreboot space to perform CPU feature programming on Application</span><br><span style="color: hsl(120, 100%, 40%);">+Processors for Intel 9th Gen (Cannon Lake) and beyond CPUs.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Today Coreboot is capable enough to handle multi-processor initialization on IA platforms.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The multi-processor initialization code has to take care of lots of duties:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+1 Bringing all cores out of reset</span><br><span style="color: hsl(120, 100%, 40%);">+2 Load latest microcode on all cores</span><br><span style="color: hsl(120, 100%, 40%);">+3 Sync latest MTRR snapshot between BSP and APs</span><br><span style="color: hsl(120, 100%, 40%);">+4 Perform sets of CPU feature programming</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPU Power & Thermal Management</span><br><span style="color: hsl(120, 100%, 40%);">+ * Overclocking</span><br><span style="color: hsl(120, 100%, 40%);">+ * Intel Trusted Execution Technology</span><br><span style="color: hsl(120, 100%, 40%);">+ * Intel Software Guard Extensions</span><br><span style="color: hsl(120, 100%, 40%);">+ * Intel Processor Trace etc.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This above CPU feature programming lists are expected to grow with current and future</span><br><span style="color: hsl(120, 100%, 40%);">+CPU complexity and there might be some cases where certain feature programming mightbe</span><br><span style="color: hsl(120, 100%, 40%);">+closed source in nature.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Platform code might need to compromise on those closed source nature of CPU programming</span><br><span style="color: hsl(120, 100%, 40%);">+if we don't plan to provide an alternate interface which can be used by Coreboot to</span><br><span style="color: hsl(120, 100%, 40%);">+get-rid of such close source CPU programming.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Proposal</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+As Coreboot is doing CPU multi-processor initialization for IA platform before FSP-S</span><br><span style="color: hsl(120, 100%, 40%);">+initialization and having all possible information about cores in terms of maximum number</span><br><span style="color: hsl(120, 100%, 40%);">+of cores, APIC ids, stack size etc. It’s also possible for Coreboot to extend its own</span><br><span style="color: hsl(120, 100%, 40%);">+support model and create a sets of APIs which later can be used by FSP to run CPU feature</span><br><span style="color: hsl(120, 100%, 40%);">+programming using Coreboot published APIs.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Due to the fact that FSP is using EFI infrastructure and need to relying on install/locate</span><br><span style="color: hsl(120, 100%, 40%);">+PPI to perform certain API call, hence Coreboot has to created MP services APIs known as </span><br><span style="color: hsl(120, 100%, 40%);">+EFI_MP_SERVICES_PPI as per PI specification volume 1, section 8.3.9.</span><br><span style="color: hsl(120, 100%, 40%);">+More details here: http://www.uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Coreboot to publish EFI_MP_SERVICES_PPI APIs</span><br><span style="color: hsl(120, 100%, 40%);">+| API | Description |</span><br><span style="color: hsl(120, 100%, 40%);">+|------------------------------|------------------------------------------------------------------|</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiGetNumberOfProcessors | Get the number of CPU's. |</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiGetProcessorInfo | Get information on a specific CPU. |</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiStartupAllAPs | Activate all of the application processors. |</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiStartupThisAP | Activate a specific application processor. |</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiSwitchBSP | Switch the boot strap processor. |</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiEnableDisableAP | Enable or disable an application processor. |</span><br><span style="color: hsl(120, 100%, 40%);">+| PeiWhoAmI | Identify the currently executing processor. |</span><br><span style="color: hsl(120, 100%, 40%);">+|------------------------------|------------------------------------------------------------------|</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Code Flow</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Here is proposed design flow with Coreboot has implemented EFI_MP_SERVICES_PPI API and FSP will make</span><br><span style="color: hsl(120, 100%, 40%);">+use of the same to perform some CPU feature programming.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+** Coreboot-FSP MP init flow **</span><br><span style="color: hsl(120, 100%, 40%);">+![alt text][Coreboot_Publish_MP_Service_API]</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[Coreboot_Publish_MP_Service_API]: Coreboot_Publish_MP_Service_API.png "Coreboot-FSP MP init flow"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Benefits</span><br><span style="color: hsl(120, 100%, 40%);">+1. Coreboot was using SkipMpInit=1 which will skip entire FSP CPU feature programming.</span><br><span style="color: hsl(120, 100%, 40%);">+With proposed model, Coreboot will make use of SkipMpInit=0 which will allow to run all</span><br><span style="color: hsl(120, 100%, 40%);">+Silicon recommended CPU programming.</span><br><span style="color: hsl(120, 100%, 40%);">+2. CPU feature programming inside FSP will be more transparent than before as it’s using</span><br><span style="color: hsl(120, 100%, 40%);">+Coreboot interfaces to execute those programming.</span><br><span style="color: hsl(120, 100%, 40%);">+3. Coreboot will have more control over running those feature programming as API optimization</span><br><span style="color: hsl(120, 100%, 40%);">+handled by Coreboot.</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25921">change 25921</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5b6096ef31d8a523c00cbad39ab9d4884e735fde </div>
<div style="display:none"> Gerrit-Change-Number: 25921 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>