<p>Matthias Gazzari has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25914">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Fix freeze during chipset lockdown on Nehalem<br><br>Remove locking of PCI device 00:00.0 registers (nehalem/finalize.c)<br>and remove setting the zeroth bit of the MSR_LT_LOCK_MEMORY = 0x2e7 MSR<br>register (model_2065x/finalize.c) to fix a frozen boot and S3 resume issue<br>which became apparent with commit d533b16669a3bacb19b2824e6b4bc76a2a18c92a.<br><br>More detailed, either setting the LSB of the 32 bit register at 0x98<br>of the PCI device 00:00.0 (in the intel_nehalem_finalize_smm function) or<br>setting the LSB of the the MSR register MSR_LT_LOCK_MEMORY = 0x2e7 (in the<br>intel_model_2065x_finalize_smm function) indepentenly causes a freeze<br>during bootup or a complete session loss on resuming from S3 as described<br>here: https://mail.coreboot.org/pipermail/coreboot/2018-April/086564.html<br><br>It seems like Nehalem CPUs do not have a MSR_LT_LOCK_MEMORY register.<br>Additionally, the "Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile<br>Processor Series, Datasheet Volume Two" indicates that registers of the<br>PCI device 00:00.0 cannot be locked manually. Instead, they can only be<br>locked by TXT, VT-d, CMD.LOCK.MEMCONFIG, ME_SM_LOCK or D_LCK.<br>Finally, the addresses and sizes of these registers were partially wrong.<br><br>Tested on Lenovo X201i with a Core i3 330M (no AES-NI, no VT-d and no TXT<br>support compared to the Core i5 and Core i7 processors of a X201).<br><br>Change-Id: I9d568d5c05807ebf7e131b3e5be8e5445476d61b<br>Signed-off-by: Matthias Gazzari <mail@qtux.eu><br>---<br>M src/cpu/intel/model_2065x/finalize.c<br>M src/cpu/intel/model_2065x/model_2065x.h<br>M src/northbridge/intel/nehalem/finalize.c<br>3 files changed, 0 insertions(+), 16 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/25914/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c</span><br><span>index 50e00bf..5e7b3d8 100644</span><br><span>--- a/src/cpu/intel/model_2065x/finalize.c</span><br><span>+++ b/src/cpu/intel/model_2065x/finalize.c</span><br><span>@@ -54,7 +54,4 @@</span><br><span> </span><br><span> /* Lock TM interupts - route thermal events to all processors */</span><br><span> msr_set_bit(MSR_MISC_PWR_MGMT, 22);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Lock memory configuration to protect SMM */</span><br><span style="color: hsl(0, 100%, 40%);">- msr_set_bit(MSR_LT_LOCK_MEMORY, 0);</span><br><span> }</span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>index 8bb3b87..f87ba77 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>@@ -39,7 +39,6 @@</span><br><span> #define ENERGY_POLICY_NORMAL 6</span><br><span> #define ENERGY_POLICY_POWERSAVE 15</span><br><span> #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span>diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c</span><br><span>index f90f937..7313840 100644</span><br><span>--- a/src/northbridge/intel/nehalem/finalize.c</span><br><span>+++ b/src/northbridge/intel/nehalem/finalize.c</span><br><span>@@ -23,18 +23,6 @@</span><br><span> </span><br><span> void intel_nehalem_finalize_smm(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */</span><br><span> MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */</span><br><span> MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25914">change 25914</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9d568d5c05807ebf7e131b3e5be8e5445476d61b </div>
<div style="display:none"> Gerrit-Change-Number: 25914 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matthias Gazzari <mail@qtux.eu> </div>