<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25897">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common: Create a new block for lpc V2<br><br>As per current code, there is already a common block for lpc ip. This<br>patch creates one more block for lpc called lpc v2 for code which is<br>still common across socs. We will move this code from soc to common<br>block version 2 so that soc code will only have changes which are<br>exactly needed for specific soc.<br><br>To use lpc from common block instead of soc, use "select<br>SOC_INTEL_COMMON_BLOCK_LPC_V2" inside Kconfig of soc.<br><br>BUG=none<br>BRANCH=none<br>TEST=code compilation is fine with different configurations.<br><br>Change-Id: Ib63708702b965535a2a3700353f3e0b460d44523<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>A src/soc/intel/common/block/lpc_v2/Kconfig<br>A src/soc/intel/common/block/lpc_v2/Makefile.inc<br>A src/soc/intel/common/block/lpc_v2/lpc.c<br>3 files changed, 232 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/25897/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/lpc_v2/Kconfig b/src/soc/intel/common/block/lpc_v2/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..f057558</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/block/lpc_v2/Kconfig</span><br><span>@@ -0,0 +1,7 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BLOCK_LPC_V2</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Use common LPC code for platform. Only soc specific code needs to</span><br><span style="color: hsl(120, 100%, 40%);">+ be implemented as per requirement.</span><br><span>diff --git a/src/soc/intel/common/block/lpc_v2/Makefile.inc b/src/soc/intel/common/block/lpc_v2/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..5ad7a9f</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/block/lpc_v2/Makefile.inc</span><br><span>@@ -0,0 +1,3 @@</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_V2)+=lpc.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_V2)+=lpc.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_V2)+=lpc.c</span><br><span>diff --git a/src/soc/intel/common/block/lpc_v2/lpc.c b/src/soc/intel/common/block/lpc_v2/lpc.c</span><br><span>new file mode 100644</span><br><span>index 0000000..01b85ed</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/block/lpc_v2/lpc.c</span><br><span>@@ -0,0 +1,222 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "chip.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <pc80/isa-dma.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <pc80/i8259.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/ioapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/itss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <reg_script.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/lpc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gen_io_dec[0] = config->gen1_dec;</span><br><span style="color: hsl(120, 100%, 40%);">+ gen_io_dec[1] = config->gen2_dec;</span><br><span style="color: hsl(120, 100%, 40%);">+ gen_io_dec[2] = config->gen3_dec;</span><br><span style="color: hsl(120, 100%, 40%);">+ gen_io_dec[3] = config->gen4_dec;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Mirror these same settings in DMI PCR */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if ENV_RAMSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_mirror_dmi_pcr_io_dec(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t io_dec_arr[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC),</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC),</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC),</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC),</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Mirror these same settings in DMI PCR */</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_enable_ioapic(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCH-LP has 120 redirection entries */</span><br><span style="color: hsl(120, 100%, 40%);">+ const int redir_entries = 120;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ set_ioapic_id((void *)IO_APIC_ADDR, 0x02);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* affirm full set of redirection table entries ("write once") */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~0x00ff0000;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= (redir_entries - 1) << 16;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Select Boot Configuration register (0x03) and</span><br><span style="color: hsl(120, 100%, 40%);">+ * use Processor System Bus (0x01) to deliver interrupts.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x00 - 0000 = Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x01 - 0001 = Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x02 - 0010 = Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x03 - 0011 = IRQ3</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x04 - 0100 = IRQ4</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x05 - 0101 = IRQ5</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x06 - 0110 = IRQ6</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x07 - 0111 = IRQ7</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x08 - 1000 = Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x09 - 1001 = IRQ9</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0A - 1010 = IRQ10</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0B - 1011 = IRQ11</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0C - 1100 = IRQ12</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0D - 1101 = Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0E - 1110 = IRQ14</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0F - 1111 = IRQ15</span><br><span style="color: hsl(120, 100%, 40%);">+ * PIRQ[n]_ROUT[7] - PIRQ Routing Control</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x80 - The PIRQ is not routed.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_pch_pirq_init(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[0] = config->pirqa_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[1] = config->pirqb_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[2] = config->pirqc_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[3] = config->pirqd_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[4] = config->pirqe_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[5] = config->pirqf_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[6] = config->pirqg_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_interrupt_routing[7] = config->pirqh_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ itss_irq_init(pch_interrupt_routing);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 int_pin = 0, int_line = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (int_pin) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1: /* INTA# */</span><br><span style="color: hsl(120, 100%, 40%);">+ int_line = config->pirqa_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2: /* INTB# */</span><br><span style="color: hsl(120, 100%, 40%);">+ int_line = config->pirqb_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 3: /* INTC# */</span><br><span style="color: hsl(120, 100%, 40%);">+ int_line = config->pirqc_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 4: /* INTD# */</span><br><span style="color: hsl(120, 100%, 40%);">+ int_line = config->pirqd_routing;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!int_line)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_misc_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setup NMI on errors, disable SERR */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = (inb(0x61)) & 0xf0;</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x61, (reg8 | (1 << 2)));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable NMI sources */</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x70, (1 << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void clock_gate_8254(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const config_t *config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!config->clock_gate_8254)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ itss_clock_gate_8254();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void lpc_soc_init(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Legacy initialization */</span><br><span style="color: hsl(120, 100%, 40%);">+ isa_dma_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_misc_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable CLKRUN_EN for power gating LPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_enable_pci_clk_cntl();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set LPC Serial IRQ mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_set_serirq_mode(SERIRQ_CONTINUOUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_set_serirq_mode(SERIRQ_QUIET);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Interrupt configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_enable_ioapic(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_pch_pirq_init(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_i8259();</span><br><span style="color: hsl(120, 100%, 40%);">+ i8259_configure_irq_trigger(9, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_gate_8254(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_mirror_dmi_pcr_io_dec();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Fill up LPC IO resource structure inside SoC directory */</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_lpc_soc_fill_io_resources(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PMC pci device gets hidden from PCI bus due to Silicon</span><br><span style="color: hsl(120, 100%, 40%);">+ * policy hence bind ACPI BASE aka ABASE (offset 0x20) with</span><br><span style="color: hsl(120, 100%, 40%);">+ * LPC IO resources to ensure that ABASE falls under PCI reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * IO memory range.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Note: Don't add any more resource with same offset 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+ * under this device space.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO |</span><br><span style="color: hsl(120, 100%, 40%);">+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25897">change 25897</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib63708702b965535a2a3700353f3e0b460d44523 </div>
<div style="display:none"> Gerrit-Change-Number: 25897 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>