<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25898">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: use common lpc code instead of soc<br><br>lpc.c file has code which is majorly common across multiple soc. In<br>previous patch, new common lpc block has been created which is lpc V2.<br><br>For cannonlake, we'll use this common code and remove redundant code<br>from soc. This will reduce line of redundant code which gets copied from<br>generation to generation<br><br>BUG=none<br>BRANCH=none<br>TEST=coreboot compiles for different configurations. Coreboot boots with<br>these changes on cannonlake.<br><br>Change-Id: Ia8fb1e5cf3133485bbd3254d27f68293976cefab<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/chip_config.c<br>D src/soc/intel/cannonlake/lpc.c<br>4 files changed, 19 insertions(+), 242 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/25898/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index a962ba4..f79059e 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -57,7 +57,7 @@</span><br><span> select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_3</span><br><span> select SOC_INTEL_COMMON_BLOCK_ITSS</span><br><span> select SOC_INTEL_COMMON_BLOCK_I2C_V2</span><br><span style="color: hsl(0, 100%, 40%);">- select SOC_INTEL_COMMON_BLOCK_LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_LPC_V2</span><br><span> select SOC_INTEL_COMMON_BLOCK_LPSS</span><br><span> select SOC_INTEL_COMMON_BLOCK_P2SB</span><br><span> select SOC_INTEL_COMMON_BLOCK_PCR</span><br><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index 94c4548..f55745a 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -16,13 +16,11 @@</span><br><span> bootblock-y += gpio.c</span><br><span> bootblock-y += memmap.c</span><br><span> bootblock-y += spi.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += lpc.c</span><br><span> bootblock-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span> romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c</span><br><span> romstage-y += chip_config.c</span><br><span> romstage-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += lpc.c</span><br><span> romstage-y += memmap.c</span><br><span> romstage-y += reset.c</span><br><span> romstage-y += spi.c</span><br><span>@@ -35,7 +33,6 @@</span><br><span> ramstage-y += gpio.c</span><br><span> ramstage-y += graphics.c</span><br><span> ramstage-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += lpc.c</span><br><span> ramstage-y += memmap.c</span><br><span> ramstage-y += nhlt.c</span><br><span> ramstage-y += pmc.c</span><br><span>diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c</span><br><span>index 123f8c2..24cc39f 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip_config.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip_config.c</span><br><span>@@ -18,7 +18,25 @@</span><br><span> #include <drivers/i2c/designware/dw_i2c.h></span><br><span> #include <intelbasecode/lockdown.h></span><br><span> #include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/lpc_lib.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve</span><br><span style="color: hsl(120, 100%, 40%);">+* certain memory range as reserved range for BIOS usage.</span><br><span style="color: hsl(120, 100%, 40%);">+* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"</span><br><span style="color: hsl(120, 100%, 40%);">+*/</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct lpc_mmio_range cnl_lpc_fixed_mmio_ranges[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 0 }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return cnl_lpc_fixed_mmio_ranges;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * This function will return SOC specific lockdown configuration.</span><br><span> * Function can return 3 possible values:</span><br><span>diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c</span><br><span>deleted file mode 100644</span><br><span>index 69a921f..0000000</span><br><span>--- a/src/soc/intel/cannonlake/lpc.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,238 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017-2018 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include "chip.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/isa-dma.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/i8259.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/ioapic.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/itss.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/pcr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reg_script.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/iomap.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/lpc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pcr_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">-* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve</span><br><span style="color: hsl(0, 100%, 40%);">-* certain memory range as reserved range for BIOS usage.</span><br><span style="color: hsl(0, 100%, 40%);">-* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"</span><br><span style="color: hsl(0, 100%, 40%);">-*/</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct lpc_mmio_range cnl_lpc_fixed_mmio_ranges[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },</span><br><span style="color: hsl(0, 100%, 40%);">- { 0, 0 }</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return cnl_lpc_fixed_mmio_ranges;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const config_t *config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- gen_io_dec[0] = config->gen1_dec;</span><br><span style="color: hsl(0, 100%, 40%);">- gen_io_dec[1] = config->gen2_dec;</span><br><span style="color: hsl(0, 100%, 40%);">- gen_io_dec[2] = config->gen3_dec;</span><br><span style="color: hsl(0, 100%, 40%);">- gen_io_dec[3] = config->gen4_dec;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Mirror these same settings in DMI PCR */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if ENV_RAMSTAGE</span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_mirror_dmi_pcr_io_dec(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t io_dec_arr[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC),</span><br><span style="color: hsl(0, 100%, 40%);">- pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC),</span><br><span style="color: hsl(0, 100%, 40%);">- pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC),</span><br><span style="color: hsl(0, 100%, 40%);">- pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC),</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">- /* Mirror these same settings in DMI PCR */</span><br><span style="color: hsl(0, 100%, 40%);">- soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_enable_ioapic(const struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- /* PCH-LP has 120 redirection entries */</span><br><span style="color: hsl(0, 100%, 40%);">- const int redir_entries = 120;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- set_ioapic_id((void *)IO_APIC_ADDR, 0x02);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* affirm full set of redirection table entries ("write once") */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= ~0x00ff0000;</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= (redir_entries - 1) << 16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Select Boot Configuration register (0x03) and</span><br><span style="color: hsl(0, 100%, 40%);">- * use Processor System Bus (0x01) to deliver interrupts.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x00 - 0000 = Reserved</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x01 - 0001 = Reserved</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x02 - 0010 = Reserved</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x03 - 0011 = IRQ3</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x04 - 0100 = IRQ4</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x05 - 0101 = IRQ5</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x06 - 0110 = IRQ6</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x07 - 0111 = IRQ7</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x08 - 1000 = Reserved</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x09 - 1001 = IRQ9</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x0A - 1010 = IRQ10</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x0B - 1011 = IRQ11</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x0C - 1100 = IRQ12</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x0D - 1101 = Reserved</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x0E - 1110 = IRQ14</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x0F - 1111 = IRQ15</span><br><span style="color: hsl(0, 100%, 40%);">- * PIRQ[n]_ROUT[7] - PIRQ Routing Control</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x80 - The PIRQ is not routed.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void soc_pch_pirq_init(const struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const config_t *config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pch_interrupt_routing[0] = config->pirqa_routing;</span><br><span style="color: hsl(0, 100%, 40%);">- pch_interrupt_routing[1] = config->pirqb_routing;</span><br><span style="color: hsl(0, 100%, 40%);">- pch_interrupt_routing[2] = config->pirqc_routing;</span><br><span style="color: hsl(0, 100%, 40%);">- pch_interrupt_routing[3] = config->pirqd_routing;</span><br><span style="color: hsl(0, 100%, 40%);">- pch_interrupt_routing[4] = config->pirqe_routing;</span><br><span style="color: hsl(0, 100%, 40%);">- pch_interrupt_routing[5] = config->pirqf_routing;</span><br><span style="color: hsl(0, 100%, 40%);">- pch_interrupt_routing[6] = config->pirqg_routing;</span><br><span style="color: hsl(0, 100%, 40%);">- pch_interrupt_routing[7] = config->pirqh_routing;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- itss_irq_init(pch_interrupt_routing);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- device_t irq_dev;</span><br><span style="color: hsl(0, 100%, 40%);">- for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {</span><br><span style="color: hsl(0, 100%, 40%);">- u8 int_pin = 0, int_line = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- switch (int_pin) {</span><br><span style="color: hsl(0, 100%, 40%);">- case 1: /* INTA# */</span><br><span style="color: hsl(0, 100%, 40%);">- int_line = config->pirqa_routing;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 2: /* INTB# */</span><br><span style="color: hsl(0, 100%, 40%);">- int_line = config->pirqb_routing;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 3: /* INTC# */</span><br><span style="color: hsl(0, 100%, 40%);">- int_line = config->pirqc_routing;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 4: /* INTD# */</span><br><span style="color: hsl(0, 100%, 40%);">- int_line = config->pirqd_routing;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!int_line)</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_misc_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t reg8;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup NMI on errors, disable SERR */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = (inb(0x61)) & 0xf0;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x61, (reg8 | (1 << 2)));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable NMI sources */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x70, (1 << 7));</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void clock_gate_8254(const struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const config_t *config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!config->clock_gate_8254)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- itss_clock_gate_8254();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void lpc_soc_init(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Legacy initialization */</span><br><span style="color: hsl(0, 100%, 40%);">- isa_dma_init();</span><br><span style="color: hsl(0, 100%, 40%);">- pch_misc_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable CLKRUN_EN for power gating LPC */</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_enable_pci_clk_cntl();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set LPC Serial IRQ mode */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_set_serirq_mode(SERIRQ_CONTINUOUS);</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_set_serirq_mode(SERIRQ_QUIET);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Interrupt configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- pch_enable_ioapic(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- soc_pch_pirq_init(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- setup_i8259();</span><br><span style="color: hsl(0, 100%, 40%);">- i8259_configure_irq_trigger(9, 1);</span><br><span style="color: hsl(0, 100%, 40%);">- clock_gate_8254(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- soc_mirror_dmi_pcr_io_dec();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Fill up LPC IO resource structure inside SoC directory */</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_lpc_soc_fill_io_resources(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * PMC pci device gets hidden from PCI bus due to Silicon</span><br><span style="color: hsl(0, 100%, 40%);">- * policy hence bind ACPI BASE aka ABASE (offset 0x20) with</span><br><span style="color: hsl(0, 100%, 40%);">- * LPC IO resources to ensure that ABASE falls under PCI reserved</span><br><span style="color: hsl(0, 100%, 40%);">- * IO memory range.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Note: Don't add any more resource with same offset 0x20</span><br><span style="color: hsl(0, 100%, 40%);">- * under this device space.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4,</span><br><span style="color: hsl(0, 100%, 40%);">- ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO |</span><br><span style="color: hsl(0, 100%, 40%);">- IORESOURCE_ASSIGNED | IORESOURCE_FIXED);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25898">change 25898</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25898"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia8fb1e5cf3133485bbd3254d27f68293976cefab </div>
<div style="display:none"> Gerrit-Change-Number: 25898 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>