<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25894">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Use common pmc utility instead of soc<br><br>Switch to common pmc utility functionality which is now common across<br>multiple socs instead of using it from cannonlake soc.<br>Removed pmutil.c file from cannonlake as we no longer need it and we'll<br>use it from common.<br>Also implemented soc dependent function in chip_config.c file which is<br>required by common pmc block.<br><br>BUG=none<br>BRANCH=none<br>TEST=code compiles with different configurations.<br><br>Change-Id: I0eb3c4c75d25554a8829da71e32438c3458ccbfb<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/chip_config.c<br>D src/soc/intel/cannonlake/pmutil.c<br>4 files changed, 20 insertions(+), 239 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/25894/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index c9b3bd3..a962ba4 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -61,7 +61,7 @@</span><br><span> select SOC_INTEL_COMMON_BLOCK_LPSS</span><br><span> select SOC_INTEL_COMMON_BLOCK_P2SB</span><br><span> select SOC_INTEL_COMMON_BLOCK_PCR</span><br><span style="color: hsl(0, 100%, 40%);">- select SOC_INTEL_COMMON_BLOCK_PMC</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_PMC_V2</span><br><span> select SOC_INTEL_COMMON_BLOCK_RTC</span><br><span> select SOC_INTEL_COMMON_BLOCK_SA</span><br><span> select SOC_INTEL_COMMON_BLOCK_SATA</span><br><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index 1e463c2..94c4548 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -11,7 +11,6 @@</span><br><span> bootblock-y += bootblock/bootblock.c</span><br><span> bootblock-y += bootblock/cpu.c</span><br><span> bootblock-y += bootblock/pch.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += pmutil.c</span><br><span> bootblock-y += bootblock/report_platform.c</span><br><span> bootblock-y += chip_config.c</span><br><span> bootblock-y += gpio.c</span><br><span>@@ -25,7 +24,6 @@</span><br><span> romstage-y += gpio.c</span><br><span> romstage-y += lpc.c</span><br><span> romstage-y += memmap.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += pmutil.c</span><br><span> romstage-y += reset.c</span><br><span> romstage-y += spi.c</span><br><span> romstage-$(CONFIG_UART_DEBUG) += uart.c</span><br><span>@@ -41,7 +39,6 @@</span><br><span> ramstage-y += memmap.c</span><br><span> ramstage-y += nhlt.c</span><br><span> ramstage-y += pmc.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += pmutil.c</span><br><span> ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c</span><br><span> ramstage-y += smmrelocate.c</span><br><span> ramstage-y += spi.c</span><br><span>@@ -52,16 +49,13 @@</span><br><span> ramstage-y += chip_config.c</span><br><span> </span><br><span> smm-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-smm-y += pmutil.c</span><br><span> smm-y += smihandler.c</span><br><span> smm-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span> postcar-y += memmap.c</span><br><span style="color: hsl(0, 100%, 40%);">-postcar-y += pmutil.c</span><br><span> postcar-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span> verstage-y += chip_config.c</span><br><span style="color: hsl(0, 100%, 40%);">-verstage-y += pmutil.c</span><br><span> verstage-y += spi.c</span><br><span> verstage-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span>diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c</span><br><span>index f3d710c..123f8c2 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip_config.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip_config.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #include <drivers/i2c/designware/dw_i2c.h></span><br><span> #include <intelbasecode/lockdown.h></span><br><span> #include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pmclib.h></span><br><span> /*</span><br><span> * This function will return SOC specific lockdown configuration.</span><br><span> * Function can return 3 possible values:</span><br><span>@@ -70,3 +71,21 @@</span><br><span> </span><br><span> return &config->gspi[0];</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ DEVTREE_CONST struct soc_intel_cannonlake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Look up the device in devicetree */</span><br><span style="color: hsl(120, 100%, 40%);">+ DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Assign to out variable */</span><br><span style="color: hsl(120, 100%, 40%);">+ *dw0 = config->gpe0_dw0;</span><br><span style="color: hsl(120, 100%, 40%);">+ *dw1 = config->gpe0_dw1;</span><br><span style="color: hsl(120, 100%, 40%);">+ *dw2 = config->gpe0_dw2;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c</span><br><span>deleted file mode 100644</span><br><span>index 951d886..0000000</span><br><span>--- a/src/soc/intel/cannonlake/pmutil.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,232 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Helper functions for dealing with power management registers</span><br><span style="color: hsl(0, 100%, 40%);">- * and the differences between PCH variants.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define __SIMPLE_DEVICE__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cbmem.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_def.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/pmclib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/rtc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <halt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <rules.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpe.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/iomap.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/lpc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/smbus.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <timer.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <security/vboot/vbnv.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "chip.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * SMI</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const char *const *soc_smi_sts_array(size_t *a)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- static const char *const smi_sts_bits[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- [BIOS_STS_BIT] = "BIOS",</span><br><span style="color: hsl(0, 100%, 40%);">- [LEGACY_USB_STS_BIT] = "LEGACY_USB",</span><br><span style="color: hsl(0, 100%, 40%);">- [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",</span><br><span style="color: hsl(0, 100%, 40%);">- [APM_STS_BIT] = "APM",</span><br><span style="color: hsl(0, 100%, 40%);">- [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",</span><br><span style="color: hsl(0, 100%, 40%);">- [PM1_STS_BIT] = "PM1",</span><br><span style="color: hsl(0, 100%, 40%);">- [GPE0_STS_BIT] = "GPE0",</span><br><span style="color: hsl(0, 100%, 40%);">- [GPIO_STS_BIT] = "GPI",</span><br><span style="color: hsl(0, 100%, 40%);">- [MCSMI_STS_BIT] = "MCSMI",</span><br><span style="color: hsl(0, 100%, 40%);">- [DEVMON_STS_BIT] = "DEVMON",</span><br><span style="color: hsl(0, 100%, 40%);">- [TCO_STS_BIT] = "TCO",</span><br><span style="color: hsl(0, 100%, 40%);">- [PERIODIC_STS_BIT] = "PERIODIC",</span><br><span style="color: hsl(0, 100%, 40%);">- [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",</span><br><span style="color: hsl(0, 100%, 40%);">- [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",</span><br><span style="color: hsl(0, 100%, 40%);">- [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",</span><br><span style="color: hsl(0, 100%, 40%);">- [MONITOR_STS_BIT] = "MONITOR",</span><br><span style="color: hsl(0, 100%, 40%);">- [SPI_SMI_STS_BIT] = "SPI",</span><br><span style="color: hsl(0, 100%, 40%);">- [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",</span><br><span style="color: hsl(0, 100%, 40%);">- [ESPI_SMI_STS_BIT] = "ESPI_SMI",</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- *a = ARRAY_SIZE(smi_sts_bits);</span><br><span style="color: hsl(0, 100%, 40%);">- return smi_sts_bits;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * TCO</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const char *const *soc_tco_sts_array(size_t *a)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- static const char *const tco_sts_bits[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- [0] = "NMI2SMI",</span><br><span style="color: hsl(0, 100%, 40%);">- [1] = "SW_TCO",</span><br><span style="color: hsl(0, 100%, 40%);">- [2] = "TCO_INT",</span><br><span style="color: hsl(0, 100%, 40%);">- [3] = "TIMEOUT",</span><br><span style="color: hsl(0, 100%, 40%);">- [7] = "NEWCENTURY",</span><br><span style="color: hsl(0, 100%, 40%);">- [8] = "BIOSWR",</span><br><span style="color: hsl(0, 100%, 40%);">- [9] = "DMISCI",</span><br><span style="color: hsl(0, 100%, 40%);">- [10] = "DMISMI",</span><br><span style="color: hsl(0, 100%, 40%);">- [12] = "DMISERR",</span><br><span style="color: hsl(0, 100%, 40%);">- [13] = "SLVSEL",</span><br><span style="color: hsl(0, 100%, 40%);">- [16] = "INTRD_DET",</span><br><span style="color: hsl(0, 100%, 40%);">- [17] = "SECOND_TO",</span><br><span style="color: hsl(0, 100%, 40%);">- [18] = "BOOT",</span><br><span style="color: hsl(0, 100%, 40%);">- [20] = "SMLINK_SLV"</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- *a = ARRAY_SIZE(tco_sts_bits);</span><br><span style="color: hsl(0, 100%, 40%);">- return tco_sts_bits;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * GPE0</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const char *const *soc_std_gpe_sts_array(size_t *a)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- static const char *const gpe_sts_bits[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- [1] = "HOTPLUG",</span><br><span style="color: hsl(0, 100%, 40%);">- [2] = "SWGPE",</span><br><span style="color: hsl(0, 100%, 40%);">- [6] = "TCO_SCI",</span><br><span style="color: hsl(0, 100%, 40%);">- [7] = "SMB_WAK",</span><br><span style="color: hsl(0, 100%, 40%);">- [9] = "PCI_EXP",</span><br><span style="color: hsl(0, 100%, 40%);">- [10] = "BATLOW",</span><br><span style="color: hsl(0, 100%, 40%);">- [11] = "PME",</span><br><span style="color: hsl(0, 100%, 40%);">- [12] = "ME",</span><br><span style="color: hsl(0, 100%, 40%);">- [13] = "PME_B0",</span><br><span style="color: hsl(0, 100%, 40%);">- [14] = "eSPI",</span><br><span style="color: hsl(0, 100%, 40%);">- [15] = "GPIO Tier-2",</span><br><span style="color: hsl(0, 100%, 40%);">- [16] = "LAN_WAKE",</span><br><span style="color: hsl(0, 100%, 40%);">- [18] = "WADT"</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- *a = ARRAY_SIZE(gpe_sts_bits);</span><br><span style="color: hsl(0, 100%, 40%);">- return gpe_sts_bits;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void pmc_set_disb(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set the DISB after DRAM init */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t disb_val;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Only care about bits [23:16] of register GEN_PMCON_A */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t *addr = (void *)(pmc_mmio_regs() + GEN_PMCON_A + 2);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- disb_val = read8(addr);</span><br><span style="color: hsl(0, 100%, 40%);">- disb_val |= (DISB >> 16);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Don't clear bits that are write-1-to-clear */</span><br><span style="color: hsl(0, 100%, 40%);">- disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);</span><br><span style="color: hsl(0, 100%, 40%);">- write8(addr, disb_val);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * PMC controller gets hidden from PCI bus</span><br><span style="color: hsl(0, 100%, 40%);">- * during FSP-Silicon init call. Hence PWRMBASE</span><br><span style="color: hsl(0, 100%, 40%);">- * can't be accessible using PCI configuration space</span><br><span style="color: hsl(0, 100%, 40%);">- * read/write.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-uint8_t *pmc_mmio_regs(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-uint16_t smbus_tco_regs(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return ALIGN_DOWN(reg16, 0x20);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t soc_reset_tco_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 tco1_sts;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 tco2_sts;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 tcobase;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- tcobase = smbus_tco_regs();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TCO Status 2 register */</span><br><span style="color: hsl(0, 100%, 40%);">- tco2_sts = inw(tcobase + TCO2_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- tco2_sts |= TCO2_STS_SECOND_TO;</span><br><span style="color: hsl(0, 100%, 40%);">- outw(tco2_sts, tcobase + TCO2_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TCO Status 1 register */</span><br><span style="color: hsl(0, 100%, 40%);">- tco1_sts = inw(tcobase + TCO1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear SECOND_TO_STS bit */</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco2_sts & TCO2_STS_SECOND_TO)</span><br><span style="color: hsl(0, 100%, 40%);">- outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return (tco2_sts << 16) | tco1_sts;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-uintptr_t soc_read_pmc_base(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return (uintptr_t)pmc_mmio_regs();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- DEVTREE_CONST struct soc_intel_cannonlake_config *config;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Look up the device in devicetree */</span><br><span style="color: hsl(0, 100%, 40%);">- DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);</span><br><span style="color: hsl(0, 100%, 40%);">- if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Assign to out variable */</span><br><span style="color: hsl(0, 100%, 40%);">- *dw0 = config->gpe0_dw0;</span><br><span style="color: hsl(0, 100%, 40%);">- *dw1 = config->gpe0_dw1;</span><br><span style="color: hsl(0, 100%, 40%);">- *dw2 = config->gpe0_dw2;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int rtc_failed(uint32_t gen_pmcon_b)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return !!(gen_pmcon_b & RTC_BATTERY_DEAD);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int soc_get_rtc_failed(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!ps) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return rtc_failed(ps->gen_pmcon_b);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int vbnv_cmos_failed(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25894">change 25894</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25894"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0eb3c4c75d25554a8829da71e32438c3458ccbfb </div>
<div style="display:none"> Gerrit-Change-Number: 25894 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>