<p>Julius Werner has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25903">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cubieboard/qemu-armv7/am335x: Add fake TTB region for consistency<br><br>All ARM architecture boards are supposed to have a TTB region for their<br>page tables. ARM systems cannot use the data cache without enabling<br>paging, so it is imperative to do that as soon as possible. They will<br>also fault on unaligned accesses when not using the cache, which breaks<br>assumptions in CBFS code.<br><br>Unfortunately, we have some old boards in various stages of disrepair in<br>the tree that don't always follow these sorts of standard conventions.<br>It's not clear whether they actually boot anymore and if anyone still<br>has the respective hardware available to maintain them. I cannot really<br>fix and test them right now, but we should at least create a fake TTB<br>section for them so that common architecture code may make the correct<br>assumptions about which regions exist.<br><br>Change-Id: I51aa259fbb7a9c0ade72db905b1762c1c721f387<br>Signed-off-by: Julius Werner <jwerner@chromium.org><br>---<br>M src/cpu/ti/am335x/memlayout.ld<br>M src/mainboard/cubietech/cubieboard/memlayout.ld<br>M src/mainboard/emulation/qemu-armv7/memlayout.ld<br>3 files changed, 9 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/25903/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/cpu/ti/am335x/memlayout.ld</span><br><span>index a6f41eb..9efb710 100644</span><br><span>--- a/src/cpu/ti/am335x/memlayout.ld</span><br><span>+++ b/src/cpu/ti/am335x/memlayout.ld</span><br><span>@@ -25,6 +25,9 @@</span><br><span>     STACK(0x4030be00, 4K)</span><br><span>        RAMSTAGE(0x80200000, 192K)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+        /* TODO: Implement MMU support and move TTB to a better location. */</span><br><span style="color: hsl(120, 100%, 40%);">+  TTB(0x81000000, 16K)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #ifdef OMAP_HEADER</span><br><span>         .header : {</span><br><span>          *(.header);</span><br><span>diff --git a/src/mainboard/cubietech/cubieboard/memlayout.ld b/src/mainboard/cubietech/cubieboard/memlayout.ld</span><br><span>index 55ba70a..b9bf10b 100644</span><br><span>--- a/src/mainboard/cubietech/cubieboard/memlayout.ld</span><br><span>+++ b/src/mainboard/cubietech/cubieboard/memlayout.ld</span><br><span>@@ -28,4 +28,7 @@</span><br><span>     DRAM_START(0x40000000)</span><br><span>       RAMSTAGE(0x40000000, 16M)</span><br><span>    ROMSTAGE(0x41000000, 108K)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+  /* TODO: Implement MMU support and move TTB to a better location. */</span><br><span style="color: hsl(120, 100%, 40%);">+  TTB(0x42000000, 16K)</span><br><span> }</span><br><span>diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld</span><br><span>index 1b3a48b..776e051 100644</span><br><span>--- a/src/mainboard/emulation/qemu-armv7/memlayout.ld</span><br><span>+++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld</span><br><span>@@ -47,4 +47,7 @@</span><br><span>       STACK(0x60000000, 64K)</span><br><span>       ROMSTAGE(0x60010000, 128K)</span><br><span>   RAMSTAGE(0x60030000, 16M)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   /* TODO: Implement MMU support and move TTB to a better location. */</span><br><span style="color: hsl(120, 100%, 40%);">+  TTB(0x61030000, 16K)</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25903">change 25903</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25903"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I51aa259fbb7a9c0ade72db905b1762c1c721f387 </div>
<div style="display:none"> Gerrit-Change-Number: 25903 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Julius Werner <jwerner@chromium.org> </div>