<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25852">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">md/SuperIO: Change DUMMY_DEV to SUPERIO_DEV for global control device<br><br>Change-Id: If3555906d359695b2eae51209cd97fbaaace7e61<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/google/beltino/onboard.h<br>M src/mainboard/google/beltino/romstage.c<br>M src/mainboard/google/jecht/onboard.h<br>M src/mainboard/google/jecht/romstage.c<br>M src/mainboard/ibase/mb899/romstage.c<br>M src/mainboard/samsung/stumpy/romstage.c<br>M src/mainboard/samsung/stumpy/smihandler.c<br>M src/mainboard/supermicro/h8dme/romstage.c<br>M src/mainboard/supermicro/h8dmr/romstage.c<br>M src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>M src/mainboard/supermicro/h8qme_fam10/romstage.c<br>M src/mainboard/via/epia-m700/romstage.c<br>12 files changed, 26 insertions(+), 26 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/25852/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/beltino/onboard.h b/src/mainboard/google/beltino/onboard.h</span><br><span>index 29da766..2e07309 100644</span><br><span>--- a/src/mainboard/google/beltino/onboard.h</span><br><span>+++ b/src/mainboard/google/beltino/onboard.h</span><br><span>@@ -31,7 +31,7 @@</span><br><span> #define IT8772F_BASE 0x2e</span><br><span> #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1)</span><br><span> #define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0)</span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span> void lan_init(void);</span><br><span>diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c</span><br><span>index 2ddb9b1..b0468f5 100644</span><br><span>--- a/src/mainboard/google/beltino/romstage.c</span><br><span>+++ b/src/mainboard/google/beltino/romstage.c</span><br><span>@@ -137,7 +137,7 @@</span><br><span> </span><br><span> /* Early SuperIO setup */</span><br><span> ite_kill_watchdog(IT8772F_GPIO_DEV);</span><br><span style="color: hsl(0, 100%, 40%);">- it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);</span><br><span> pch_enable_lpc();</span><br><span> ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span> </span><br><span>diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h</span><br><span>index a911fe6..d92aa16 100644</span><br><span>--- a/src/mainboard/google/jecht/onboard.h</span><br><span>+++ b/src/mainboard/google/jecht/onboard.h</span><br><span>@@ -50,6 +50,6 @@</span><br><span> #define IT8772F_BASE 0x2e</span><br><span> #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1)</span><br><span> #define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0)</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c</span><br><span>index 6203a1e..c3a5720 100644</span><br><span>--- a/src/mainboard/google/jecht/romstage.c</span><br><span>+++ b/src/mainboard/google/jecht/romstage.c</span><br><span>@@ -54,7 +54,7 @@</span><br><span> void mainboard_pre_console_init(void)</span><br><span> {</span><br><span> /* Early SuperIO setup */</span><br><span style="color: hsl(0, 100%, 40%);">- it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);</span><br><span> ite_kill_watchdog(IT8772F_GPIO_DEV);</span><br><span> ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span> </span><br><span>diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c</span><br><span>index 1b8bb95..dd384ac 100644</span><br><span>--- a/src/mainboard/ibase/mb899/romstage.c</span><br><span>+++ b/src/mainboard/ibase/mb899/romstage.c</span><br><span>@@ -37,7 +37,7 @@</span><br><span> #include <southbridge/intel/i82801gx/i82801gx.h></span><br><span> </span><br><span> #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DUMMY_DEV PNP_DEV(0x4e, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV PNP_DEV(0x4e, 0)</span><br><span> </span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span>@@ -63,7 +63,7 @@</span><br><span> {</span><br><span> pnp_devfn_t dev;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- dev = DUMMY_DEV;</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = SUPERIO_DEV;</span><br><span> pnp_enter_conf_state(dev);</span><br><span> </span><br><span> pnp_write_config(dev, 0x24, 0xc4); // PNPCVS</span><br><span>diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c</span><br><span>index 1b5d2ae..0da658c 100644</span><br><span>--- a/src/mainboard/samsung/stumpy/romstage.c</span><br><span>+++ b/src/mainboard/samsung/stumpy/romstage.c</span><br><span>@@ -52,7 +52,7 @@</span><br><span> #endif</span><br><span> #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define DUMMY_DEV PNP_DEV(0x2e, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV PNP_DEV(0x2e, 0)</span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)</span><br><span> #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)</span><br><span> </span><br><span>@@ -123,17 +123,17 @@</span><br><span> * GPIO10 as USBPWRON12#</span><br><span> * GPIO12 as USBPWRON13#</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- it8772f_gpio_setup(DUMMY_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05);</span><br><span style="color: hsl(120, 100%, 40%);">+ it8772f_gpio_setup(SUPERIO_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05);</span><br><span> </span><br><span> /*</span><br><span> * GPIO22 as wake SCI#</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- it8772f_gpio_setup(DUMMY_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04);</span><br><span style="color: hsl(120, 100%, 40%);">+ it8772f_gpio_setup(SUPERIO_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04);</span><br><span> </span><br><span> /*</span><br><span> * GPIO32 as EXTSMI#</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- it8772f_gpio_setup(DUMMY_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04);</span><br><span style="color: hsl(120, 100%, 40%);">+ it8772f_gpio_setup(SUPERIO_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04);</span><br><span> </span><br><span> /*</span><br><span> * GPIO45 as LED_POWER#</span><br><span>@@ -147,8 +147,8 @@</span><br><span> * GPIO51 as USBPWRON8#</span><br><span> * GPIO52 as USBPWRON1#</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- it8772f_gpio_setup(DUMMY_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06);</span><br><span style="color: hsl(0, 100%, 40%);">- it8772f_gpio_setup(DUMMY_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+ it8772f_gpio_setup(SUPERIO_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06);</span><br><span style="color: hsl(120, 100%, 40%);">+ it8772f_gpio_setup(SUPERIO_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00);</span><br><span> }</span><br><span> </span><br><span> void mainboard_fill_pei_data(struct pei_data *pei_data)</span><br><span>@@ -258,7 +258,7 @@</span><br><span> setup_sio_gpios();</span><br><span> </span><br><span> /* Early SuperIO setup */</span><br><span style="color: hsl(0, 100%, 40%);">- it8772f_ac_resume_southbridge(DUMMY_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ it8772f_ac_resume_southbridge(SUPERIO_DEV);</span><br><span> ite_kill_watchdog(GPIO_DEV);</span><br><span> ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span> }</span><br><span>diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c</span><br><span>index 00148f2..ad27bce 100644</span><br><span>--- a/src/mainboard/samsung/stumpy/smihandler.c</span><br><span>+++ b/src/mainboard/samsung/stumpy/smihandler.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> </span><br><span> /* Include for SIO helper functions */</span><br><span> #include <superio/ite/it8772f/it8772f.h></span><br><span style="color: hsl(0, 100%, 40%);">-#define DUMMY_DEV PNP_DEV(0x2e, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV PNP_DEV(0x2e, 0)</span><br><span> </span><br><span> /*</span><br><span> * Change LED_POWER# (SIO GPIO 45) state based on sleep type.</span><br><span>@@ -36,14 +36,14 @@</span><br><span> switch (slp_typ) {</span><br><span> case ACPI_S3:</span><br><span> case ACPI_S4:</span><br><span style="color: hsl(0, 100%, 40%);">- it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1 << 5) /* select */,</span><br><span style="color: hsl(120, 100%, 40%);">+ it8772f_gpio_led(SUPERIO_DEV, 4 /* set */, (0x1 << 5) /* select */,</span><br><span> (0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */,</span><br><span> (0x1 << 5) /* output */, 0x00, /* 0 = Alternate function */</span><br><span> SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);</span><br><span> break;</span><br><span> </span><br><span> case ACPI_S5:</span><br><span style="color: hsl(0, 100%, 40%);">- it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1 << 5) /* select */,</span><br><span style="color: hsl(120, 100%, 40%);">+ it8772f_gpio_led(SUPERIO_DEV, 4 /* set */, (0x1 << 5) /* select */,</span><br><span> 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */,</span><br><span> (0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */,</span><br><span> SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);</span><br><span>diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c</span><br><span>index 9deb940..13cb038 100644</span><br><span>--- a/src/mainboard/supermicro/h8dme/romstage.c</span><br><span>+++ b/src/mainboard/supermicro/h8dme/romstage.c</span><br><span>@@ -36,7 +36,7 @@</span><br><span> #include "northbridge/amd/amdk8/setup_resource_map.c"</span><br><span> </span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DUMMY_DEV PNP_DEV(0x2e, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV PNP_DEV(0x2e, 0)</span><br><span> </span><br><span> unsigned get_sbdn(unsigned bus);</span><br><span> </span><br><span>@@ -140,7 +140,7 @@</span><br><span> if (bist == 0)</span><br><span> bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- winbond_set_clksel_48(DUMMY_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ winbond_set_clksel_48(SUPERIO_DEV);</span><br><span> winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span> </span><br><span> console_init();</span><br><span>diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c</span><br><span>index 9da1ab5..a766f01 100644</span><br><span>--- a/src/mainboard/supermicro/h8dmr/romstage.c</span><br><span>+++ b/src/mainboard/supermicro/h8dmr/romstage.c</span><br><span>@@ -39,7 +39,7 @@</span><br><span> #include "northbridge/amd/amdk8/setup_resource_map.c"</span><br><span> </span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DUMMY_DEV PNP_DEV(0x2e, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV PNP_DEV(0x2e, 0)</span><br><span> </span><br><span> unsigned get_sbdn(unsigned bus);</span><br><span> </span><br><span>@@ -120,7 +120,7 @@</span><br><span> if (bist == 0)</span><br><span> bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- winbond_set_clksel_48(DUMMY_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ winbond_set_clksel_48(SUPERIO_DEV);</span><br><span> winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span> </span><br><span> console_init();</span><br><span>diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c</span><br><span>index fa22952..c360389 100644</span><br><span>--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c</span><br><span>+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c</span><br><span>@@ -50,7 +50,7 @@</span><br><span> #include "southbridge/nvidia/mcp55/early_setup_car.c"</span><br><span> </span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DUMMY_DEV PNP_DEV(0x2e, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV PNP_DEV(0x2e, 0)</span><br><span> </span><br><span> void activate_spd_rom(const struct mem_controller *ctrl);</span><br><span> int spd_read_byte(unsigned device, unsigned address);</span><br><span>@@ -130,7 +130,7 @@</span><br><span> </span><br><span> post_code(0x32);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- winbond_set_clksel_48(DUMMY_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ winbond_set_clksel_48(SUPERIO_DEV);</span><br><span> winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span> </span><br><span> console_init();</span><br><span>diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c</span><br><span>index 8c693a8..723a665 100644</span><br><span>--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c</span><br><span>+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c</span><br><span>@@ -49,7 +49,7 @@</span><br><span> #include "southbridge/nvidia/mcp55/early_setup_car.c"</span><br><span> </span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DUMMY_DEV PNP_DEV(0x2e, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV PNP_DEV(0x2e, 0)</span><br><span> </span><br><span> #define SMBUS_SWITCH1 0x70</span><br><span> #define SMBUS_SWITCH2 0x72</span><br><span>@@ -195,7 +195,7 @@</span><br><span> </span><br><span> post_code(0x32);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- winbond_set_clksel_48(DUMMY_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ winbond_set_clksel_48(SUPERIO_DEV);</span><br><span> winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span> </span><br><span> console_init();</span><br><span>diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c</span><br><span>index faf87c7..0aeec7a 100644</span><br><span>--- a/src/mainboard/via/epia-m700/romstage.c</span><br><span>+++ b/src/mainboard/via/epia-m700/romstage.c</span><br><span>@@ -41,7 +41,7 @@</span><br><span> #include <superio/winbond/w83697hf/w83697hf.h></span><br><span> </span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DUMMY_DEV PNP_DEV(0x2e, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV PNP_DEV(0x2e, 0)</span><br><span> </span><br><span> /*</span><br><span> * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:</span><br><span>@@ -378,7 +378,7 @@</span><br><span> */</span><br><span> pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);</span><br><span> /* EmbedComInit(); */</span><br><span style="color: hsl(0, 100%, 40%);">- winbond_set_clksel_48(DUMMY_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ winbond_set_clksel_48(SUPERIO_DEV);</span><br><span> winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span> /* enable_vx800_serial(); */</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25852">change 25852</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25852"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If3555906d359695b2eae51209cd97fbaaace7e61 </div>
<div style="display:none"> Gerrit-Change-Number: 25852 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>