<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25879">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">southbridge/nvidia: Remove spaces before/after parenthesis<br><br>Change-Id: I94a87d631c9336b861523592ff217fe823436b36<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/nvidia/ck804/acpi/ck804.asl<br>M src/southbridge/nvidia/mcp55/early_setup_car.c<br>M src/southbridge/nvidia/mcp55/lpc.c<br>M src/southbridge/nvidia/mcp55/smbus.h<br>4 files changed, 6 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/25879/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/nvidia/ck804/acpi/ck804.asl b/src/southbridge/nvidia/ck804/acpi/ck804.asl</span><br><span>index aac7ea8..4a83b84 100644</span><br><span>--- a/src/southbridge/nvidia/ck804/acpi/ck804.asl</span><br><span>+++ b/src/southbridge/nvidia/ck804/acpi/ck804.asl</span><br><span>@@ -54,7 +54,7 @@</span><br><span> </span><br><span> /* set "B", external (PCI) APIC interrupts */</span><br><span> Name (PRSB, ResourceTemplate () {</span><br><span style="color: hsl(0, 100%, 40%);">-     Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) {</span><br><span>                 16, 17, 18, 19,</span><br><span>      }</span><br><span> })</span><br><span>@@ -93,7 +93,7 @@</span><br><span> </span><br><span> /* set "C", southbridge APIC interrupts */</span><br><span> Name (PRSC, ResourceTemplate () {</span><br><span style="color: hsl(0, 100%, 40%);">-    Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) {</span><br><span>                 20, 21, 22, 23,</span><br><span>      }</span><br><span> })</span><br><span>diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c</span><br><span>index 8019a8e..6ddd59e 100644</span><br><span>--- a/src/southbridge/nvidia/mcp55/early_setup_car.c</span><br><span>+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c</span><br><span>@@ -83,7 +83,7 @@</span><br><span>     };</span><br><span> </span><br><span>       int j;</span><br><span style="color: hsl(0, 100%, 40%);">-  for (j = 0; j < mcp55_num; j++ ) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (j = 0; j < mcp55_num; j++) {</span><br><span>                 setup_resource_map_offset(ctrl_devport_conf,</span><br><span>                         ARRAY_SIZE(ctrl_devport_conf),</span><br><span>                       PCI_DEV(busn[j], devn[j], 0) , io_base[j]);</span><br><span>@@ -100,7 +100,7 @@</span><br><span>    };</span><br><span> </span><br><span>       int j;</span><br><span style="color: hsl(0, 100%, 40%);">-  for (j = 0; j < mcp55_num; j++ ) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (j = 0; j < mcp55_num; j++) {</span><br><span>                 setup_resource_map_offset(ctrl_devport_conf_clear,</span><br><span>                   ARRAY_SIZE(ctrl_devport_conf_clear),</span><br><span>                         PCI_DEV(busn[j], devn[j], 0) , io_base[j]);</span><br><span>diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c</span><br><span>index eeb6c1b..180b9a8 100644</span><br><span>--- a/src/southbridge/nvidia/mcp55/lpc.c</span><br><span>+++ b/src/southbridge/nvidia/mcp55/lpc.c</span><br><span>@@ -131,7 +131,7 @@</span><br><span>       if (nmi_option)</span><br><span>              byte &= ~(1 << 7); /* Set NMI. */</span><br><span>  else</span><br><span style="color: hsl(0, 100%, 40%);">-            byte |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */</span><br><span style="color: hsl(120, 100%, 40%);">+             byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */</span><br><span>     if (byte != byte_old)</span><br><span>                outb(byte, 0x70);</span><br><span> </span><br><span>diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h</span><br><span>index a588a09..274ccfe 100644</span><br><span>--- a/src/southbridge/nvidia/mcp55/smbus.h</span><br><span>+++ b/src/southbridge/nvidia/mcp55/smbus.h</span><br><span>@@ -45,7 +45,7 @@</span><br><span>               smbus_delay();</span><br><span> </span><br><span>           val = inb(smbus_io_base + SMBHSTSTAT);</span><br><span style="color: hsl(0, 100%, 40%);">-          if ( (val & 0xff) != 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+         if ((val & 0xff) != 0) {</span><br><span>                         return 0;</span><br><span>            }</span><br><span>    } while (--loops);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25879">change 25879</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25879"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I94a87d631c9336b861523592ff217fe823436b36 </div>
<div style="display:none"> Gerrit-Change-Number: 25879 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>