<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25839">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/pcengines/apu2/spd: Remove unneeded whitespaces<br><br>Change-Id: I0c59cefa4067d3fc01b8425184e10d3caf1c81ac<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex<br>M src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex<br>2 files changed, 8 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/25839/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex b/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex</span><br><span>index a70db53..835d258 100644</span><br><span>--- a/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex</span><br><span>+++ b/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex</span><br><span>@@ -44,7 +44,7 @@</span><br><span> 00</span><br><span> </span><br><span> # 7 Module Organization</span><br><span style="color: hsl(0, 100%, 40%);">-# bits[2:0]: 1 = 8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+# bits[2:0]: 1 = 8 bits</span><br><span> # bits[2:0]: 2 = 16 bits</span><br><span> # bits[5:3]: 0 = 1 Rank</span><br><span> # bits[7:6]: reserved</span><br><span>@@ -103,7 +103,7 @@</span><br><span> 30</span><br><span> </span><br><span> # 20 Minimum Row Precharge Delay Time (tRPmin)</span><br><span style="color: hsl(0, 100%, 40%);">-# 0x6C = 13.5ns - </span><br><span style="color: hsl(120, 100%, 40%);">+# 0x6C = 13.5ns -</span><br><span> # 0x69 = 13.125 ns - DDR3-1333</span><br><span> 69</span><br><span> </span><br><span>@@ -190,7 +190,7 @@</span><br><span> 86</span><br><span> </span><br><span> # 42 - 47 (reserved)</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00</span><br><span> </span><br><span> # 48 - 55 (reserved)</span><br><span> 00 00 00 00 00 00 00 00</span><br><span>@@ -212,7 +212,7 @@</span><br><span> # bits[4:0]: 0 = Reference Raw card A used</span><br><span> # bits[6:5]: 0 = revision 0</span><br><span> # bit7 : 0 = Reference raw cards A through AL</span><br><span style="color: hsl(0, 100%, 40%);">-# revision B4 </span><br><span style="color: hsl(120, 100%, 40%);">+# revision B4</span><br><span> 61</span><br><span> </span><br><span> # 63 Address Mapping from Edge Connector to DRAM</span><br><span>@@ -261,4 +261,3 @@</span><br><span> </span><br><span> # 126 - 127: Cyclical Redundancy Code</span><br><span> b6 73</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>diff --git a/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex b/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex</span><br><span>index ac6b4c6..adc5438 100644</span><br><span>--- a/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex</span><br><span>+++ b/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex</span><br><span>@@ -1,4 +1,4 @@</span><br><span style="color: hsl(0, 100%, 40%);">-# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix </span><br><span style="color: hsl(120, 100%, 40%);">+# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix</span><br><span> </span><br><span> # SPD contents for APU 4GB DDR3 ECC (1333MHz PC1333) soldered down</span><br><span> # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage</span><br><span>@@ -102,7 +102,7 @@</span><br><span> 30</span><br><span> </span><br><span> # 20 Minimum Row Precharge Delay Time (tRPmin)</span><br><span style="color: hsl(0, 100%, 40%);">-# 0x6C = 13.5ns - </span><br><span style="color: hsl(120, 100%, 40%);">+# 0x6C = 13.5ns -</span><br><span> # 0x69 = 13.125 ns - DDR3-1333</span><br><span> 69</span><br><span> </span><br><span>@@ -186,7 +186,7 @@</span><br><span> 86</span><br><span> </span><br><span> # 42 - 47 (reserved)</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00</span><br><span> </span><br><span> # 48 - 55 (reserved)</span><br><span> 00 00 00 00 00 00 00 00</span><br><span>@@ -208,7 +208,7 @@</span><br><span> # bits[4:0]: 0 = Reference Raw card A used</span><br><span> # bits[6:5]: 0 = revision 0</span><br><span> # bit7 : 0 = Reference raw cards A through AL</span><br><span style="color: hsl(0, 100%, 40%);">-# revision B4 </span><br><span style="color: hsl(120, 100%, 40%);">+# revision B4</span><br><span> 61</span><br><span> </span><br><span> # 63 Address Mapping from Edge Connector to DRAM</span><br><span>@@ -255,7 +255,3 @@</span><br><span> </span><br><span> # 126 - 127: Cyclical Redundancy Code</span><br><span> 67 94</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25839">change 25839</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0c59cefa4067d3fc01b8425184e10d3caf1c81ac </div>
<div style="display:none"> Gerrit-Change-Number: 25839 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>