<p>Bora Guvendik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25802">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP] soc/intel/apollolake: Use bootblock common stage<br><br>Change apollolake bootcode to use common bootblock stage<br><br>Change-Id: I319453c902632f26eec63ab9c1e9bb6956b466fb<br>Signed-off-by: Bora Guvendik <bora.guvendik@intel.com><br>---<br>M src/soc/intel/apollolake/Kconfig<br>M src/soc/intel/apollolake/Makefile.inc<br>A src/soc/intel/apollolake/bootblock/cpu.c<br>R src/soc/intel/apollolake/bootblock/pch.c<br>A src/soc/intel/apollolake/include/soc/pch.h<br>5 files changed, 63 insertions(+), 23 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/25802/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig</span><br><span>index a9b90c4..a5842ec 100644</span><br><span>--- a/src/soc/intel/apollolake/Kconfig</span><br><span>+++ b/src/soc/intel/apollolake/Kconfig</span><br><span>@@ -66,6 +66,8 @@</span><br><span> select SA_ENABLE_IMR</span><br><span> select SOC_INTEL_COMMON</span><br><span> select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE_BOOTBLOCK</span><br><span> select SOC_INTEL_COMMON_BLOCK</span><br><span> select SOC_INTEL_COMMON_BLOCK_ACPI</span><br><span> select SOC_INTEL_COMMON_BLOCK_CPU</span><br><span>diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc</span><br><span>index 65df559..854f328 100644</span><br><span>--- a/src/soc/intel/apollolake/Makefile.inc</span><br><span>+++ b/src/soc/intel/apollolake/Makefile.inc</span><br><span>@@ -8,7 +8,8 @@</span><br><span> subdirs-y += ../../../cpu/x86/tsc</span><br><span> subdirs-y += ../../../cpu/x86/cache</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += bootblock/bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock/cpu.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock/pch.c</span><br><span> bootblock-y += car.c</span><br><span> bootblock-y += heci.c</span><br><span> bootblock-y += gspi.c</span><br><span>diff --git a/src/soc/intel/apollolake/bootblock/cpu.c b/src/soc/intel/apollolake/bootblock/cpu.c</span><br><span>new file mode 100644</span><br><span>index 0000000..9568750</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/apollolake/bootblock/cpu.c</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/fast_spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_cpu_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_cache_bios_region();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/pch.c</span><br><span>similarity index 84%</span><br><span>rename from src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>rename to src/soc/intel/apollolake/bootblock/pch.c</span><br><span>index 63b023d..4a4e793 100644</span><br><span>--- a/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>+++ b/src/soc/intel/apollolake/bootblock/pch.c</span><br><span>@@ -15,23 +15,18 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> #include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/bootblock.h></span><br><span> #include <bootblock_common.h></span><br><span> #include <device/pci.h></span><br><span> #include <intelblocks/cpulib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/fast_spi.h></span><br><span> #include <intelblocks/pcr.h></span><br><span> #include <intelblocks/rtc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/systemagent.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <soc/iomap.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/cpu.h></span><br><span> #include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/uart.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/uart.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <spi-generic.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <timestamp.h></span><br><span> </span><br><span> static const struct pad_config tpm_spi_configs[] = {</span><br><span> #if IS_ENABLED(CONFIG_SOC_INTEL_GLK)</span><br><span>@@ -47,12 +42,10 @@</span><br><span> gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void bootblock_c_entry(uint64_t base_timestamp)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_p2sbbar(void)</span><br><span> {</span><br><span> device_t dev;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_systemagent_early_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> dev = PCH_DEV_P2SB;</span><br><span> /* BAR and MMIO enable for PCR-Space, so that GPIOs can be configured */</span><br><span> pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);</span><br><span>@@ -65,11 +58,6 @@</span><br><span> pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS);</span><br><span> pci_write_config16(dev, PCI_COMMAND,</span><br><span> PCI_COMMAND_IO | PCI_COMMAND_MASTER);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- enable_rtc_upper_bank();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Call lib/bootblock.c main */</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_main_with_timestamp(base_timestamp);</span><br><span> }</span><br><span> </span><br><span> static void enable_pmcbar(void)</span><br><span>@@ -87,28 +75,30 @@</span><br><span> PCI_COMMAND_MASTER);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_soc_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_pch_early_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_p2sbbar();</span><br><span style="color: hsl(120, 100%, 40%);">+ </span><br><span style="color: hsl(120, 100%, 40%);">+ enable_rtc_upper_bank();</span><br><span> </span><br><span> enable_pmcbar();</span><br><span> </span><br><span> /* Clear global reset promotion bit */</span><br><span> pmc_global_reset_enable(0);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Prepare UART for serial console. */</span><br><span> if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))</span><br><span> pch_uart_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_pch_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg; </span><br><span> </span><br><span> if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI))</span><br><span> tpm_enable();</span><br><span> </span><br><span> enable_pm_timer_emulation();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_cache_bios_region();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Initialize GPE for use as interrupt status */</span><br><span> pmc_gpe_init();</span><br><span> </span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/pch.h b/src/soc/intel/apollolake/include/soc/pch.h</span><br><span>new file mode 100644</span><br><span>index 0000000..901f66e</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/pch.h</span><br><span>@@ -0,0 +1,23 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_CANNONLAKE_PCH_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_CANNONLAKE_PCH_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_uart_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25802">change 25802</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25802"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I319453c902632f26eec63ab9c1e9bb6956b466fb </div>
<div style="display:none"> Gerrit-Change-Number: 25802 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Bora Guvendik <bora.guvendik@intel.com> </div>