<p>Srinidhi N Kaushik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25757">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/intel: Update FSP Header files per v2.0.2<br><br>Update FSP header files to match GLK FSP Reference Code Release v2.0.0<br><br>Change-Id: I78d064db41a54d97e98d6e44e0832724127e5bfc<br>Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>2 files changed, 76 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/25757/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h</span><br><span>index 4559e22..0bcb44c 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h</span><br><span>@@ -993,7 +993,12 @@</span><br><span> **/</span><br><span> UINT32 RootPort5Perst;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x017C</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x017C - CpuPeiApWakeupBufferAddr</span><br><span style="color: hsl(120, 100%, 40%);">+ Address for PERST pin for Rootport 5.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 CpuPeiApWakeupBufferAddr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0180</span><br><span> **/</span><br><span> UINT8 ReservedFspmUpd[4];</span><br><span> } FSP_M_CONFIG;</span><br><span>@@ -1014,9 +1019,9 @@</span><br><span> **/</span><br><span> FSP_M_CONFIG FspmConfig;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0180</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0184</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace1[134];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace1[130];</span><br><span> </span><br><span> /** Offset 0x0206</span><br><span> **/</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>index cc50058..970f0e2 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>@@ -1701,11 +1701,72 @@</span><br><span> **/</span><br><span> UINT8 ProcessorTraceOutputScheme;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03A9</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03A9 - USB PDO Programming</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming</span><br><span style="color: hsl(120, 100%, 40%);">+ during later phase. 1: enable, 0: disable</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: enable, 0: disable</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspsUpd[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UsbPdoProgramming;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03AA</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspsUpd[6];</span><br><span> } FSP_S_CONFIG;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp S SGX Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03C0</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Signature;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03C4 - Selective enable SGX</span><br><span style="color: hsl(120, 100%, 40%);">+ Selective enable SGX. 0xFFFF(Default).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 SelectiveEnableSgx;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03C6 - SGX debug mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Select SGX mode. 0:Disable(default), 1:Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable(default), 1:Enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SgxDebugMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03C7 - SGX Launch Control Policy Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default)</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Intel locked , 1:Unlocked mode(default) , 2: Locked mode</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SgxLcp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03C8 - LE KeyHash0</span><br><span style="color: hsl(120, 100%, 40%);">+ LE KeyHash0. 0x0(Default).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 SgxLePubKeyHash0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03D0 - LE KeyHash1</span><br><span style="color: hsl(120, 100%, 40%);">+ LE KeyHash1. 0x0(Default).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 SgxLePubKeyHash1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03D8 - LE KeyHash2</span><br><span style="color: hsl(120, 100%, 40%);">+ LE KeyHash2. 0x0(Default).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 SgxLePubKeyHash2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03E0</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace8[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03F0 - LE KeyHash3</span><br><span style="color: hsl(120, 100%, 40%);">+ LE KeyHash3. 0x0(Default).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 SgxLePubKeyHash3;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03F8</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspsSgxUpd[6];</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_S_SGX_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /** Fsp S UPD Configuration</span><br><span> **/</span><br><span> typedef struct {</span><br><span>@@ -1720,7 +1781,11 @@</span><br><span> </span><br><span> /** Offset 0x03B0</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace7[78];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace7[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03C0</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_S_SGX_CONFIG FspsSgxConfig;</span><br><span> </span><br><span> /** Offset 0x03FE</span><br><span> **/</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25757">change 25757</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I78d064db41a54d97e98d6e44e0832724127e5bfc </div>
<div style="display:none"> Gerrit-Change-Number: 25757 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> </div>