<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25726">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structure<br><br>The GPIO definition structure has evolved to a point where it's no longer<br>specific to stoneyridge, though probably still specific to AMD. Therefore,<br>rename the GPIO declaration structure removing stoneyridge from it.<br><br>BUG=b:72875858<br>TEST=Build kahlee, grunt, gardenia.<br><br>Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/mainboard/amd/gardenia/bootblock/bootblock.c<br>M src/mainboard/amd/gardenia/gpio.c<br>M src/mainboard/amd/gardenia/gpio.h<br>M src/mainboard/amd/gardenia/mainboard.c<br>M src/mainboard/google/kahlee/bootblock/bootblock.c<br>M src/mainboard/google/kahlee/mainboard.c<br>M src/mainboard/google/kahlee/variants/baseboard/gpio.c<br>M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h<br>M src/mainboard/google/kahlee/variants/kahlee/gpio.c<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>11 files changed, 25 insertions(+), 25 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25726/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/amd/gardenia/bootblock/bootblock.c b/src/mainboard/amd/gardenia/bootblock/bootblock.c</span><br><span>index cb2a135..140bc07 100644</span><br><span>--- a/src/mainboard/amd/gardenia/bootblock/bootblock.c</span><br><span>+++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c</span><br><span>@@ -21,7 +21,7 @@</span><br><span> void bootblock_mainboard_early_init(void)</span><br><span> {</span><br><span> size_t num_gpios;</span><br><span style="color: hsl(0, 100%, 40%);">- const struct soc_amd_stoneyridge_gpio *gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_amd_gpio *gpios;</span><br><span> gpios = early_gpio_table(&num_gpios);</span><br><span> sb_program_gpios(gpios, num_gpios);</span><br><span> }</span><br><span>diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c</span><br><span>index cb10e74..acd4edd 100644</span><br><span>--- a/src/mainboard/amd/gardenia/gpio.c</span><br><span>+++ b/src/mainboard/amd/gardenia/gpio.c</span><br><span>@@ -26,7 +26,7 @@</span><br><span> * bootblock while GPIO pins used only by the OS should be initialized at</span><br><span> * ramstage.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio gpio_set_stage_reset[] = {</span><br><span> /* NFC PU */</span><br><span> PAD_GPO(GPIO_64, HIGH),</span><br><span> /* PCIe presence detect */</span><br><span>@@ -47,7 +47,7 @@</span><br><span> PAD_NF(GPIO_143, UART1_TXD, PULL_NONE),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio gpio_set_stage_ram[] = {</span><br><span> /* BT radio disable */</span><br><span> PAD_GPO(GPIO_14, HIGH),</span><br><span> /* NFC wake */</span><br><span>@@ -58,13 +58,13 @@</span><br><span> PAD_GPO(GPIO_70, HIGH),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio *early_gpio_table(size_t *size)</span><br><span> {</span><br><span> *size = ARRAY_SIZE(gpio_set_stage_reset);</span><br><span> return gpio_set_stage_reset;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio *gpio_table(size_t *size)</span><br><span> {</span><br><span> *size = ARRAY_SIZE(gpio_set_stage_ram);</span><br><span> return gpio_set_stage_ram;</span><br><span>diff --git a/src/mainboard/amd/gardenia/gpio.h b/src/mainboard/amd/gardenia/gpio.h</span><br><span>index f386944..1d3a8a2 100644</span><br><span>--- a/src/mainboard/amd/gardenia/gpio.h</span><br><span>+++ b/src/mainboard/amd/gardenia/gpio.h</span><br><span>@@ -16,7 +16,7 @@</span><br><span> #ifndef MAINBOARD_GPIO_H</span><br><span> #define MAINBOARD_GPIO_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size);</span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio *early_gpio_table(size_t *size);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio *gpio_table(size_t *size);</span><br><span> </span><br><span> #endif /* MAINBOARD_GPIO_H */</span><br><span>diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c</span><br><span>index 71fa257..9853803 100644</span><br><span>--- a/src/mainboard/amd/gardenia/mainboard.c</span><br><span>+++ b/src/mainboard/amd/gardenia/mainboard.c</span><br><span>@@ -81,7 +81,7 @@</span><br><span> static void mainboard_init(void *chip_info)</span><br><span> {</span><br><span> size_t num_gpios;</span><br><span style="color: hsl(0, 100%, 40%);">- const struct soc_amd_stoneyridge_gpio *gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_amd_gpio *gpios;</span><br><span> gpios = gpio_table(&num_gpios);</span><br><span> sb_program_gpios(gpios, num_gpios);</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>index 641287c..843bf4e 100644</span><br><span>--- a/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>@@ -23,7 +23,7 @@</span><br><span> void bootblock_mainboard_early_init(void)</span><br><span> {</span><br><span> size_t num_gpios;</span><br><span style="color: hsl(0, 100%, 40%);">- const struct soc_amd_stoneyridge_gpio *gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_amd_gpio *gpios;</span><br><span> </span><br><span> /* Enable the EC as soon as we have visibility */</span><br><span> mainboard_ec_init();</span><br><span>diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c</span><br><span>index e82569e..cd37c90 100644</span><br><span>--- a/src/mainboard/google/kahlee/mainboard.c</span><br><span>+++ b/src/mainboard/google/kahlee/mainboard.c</span><br><span>@@ -159,7 +159,7 @@</span><br><span> size_t num;</span><br><span> int boardid = board_id();</span><br><span> size_t num_gpios;</span><br><span style="color: hsl(0, 100%, 40%);">- const struct soc_amd_stoneyridge_gpio *gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_amd_gpio *gpios;</span><br><span> </span><br><span> printk(BIOS_INFO, "Board ID: %d\n", boardid);</span><br><span> </span><br><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>index 6b81b3e..1a03acd 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> * bootblock while GPIO pins used only by the OS should be initialized at</span><br><span> * ramstage.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset_old[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const static struct soc_amd_gpio gpio_set_stage_reset_old[] = {</span><br><span> /* GPIO_0 - EC_PCH_PWR_BTN_ODL */</span><br><span> PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP),</span><br><span> </span><br><span>@@ -196,7 +196,7 @@</span><br><span> PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const static struct soc_amd_gpio gpio_set_stage_reset[] = {</span><br><span> /* GPIO_0 - EC_PCH_PWR_BTN_ODL */</span><br><span> PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP),</span><br><span> </span><br><span>@@ -370,7 +370,7 @@</span><br><span> PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram_old[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const static struct soc_amd_gpio gpio_set_stage_ram_old[] = {</span><br><span> /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */</span><br><span> PAD_NF(GPIO_2, WAKE_L, PULL_UP),</span><br><span> </span><br><span>@@ -429,7 +429,7 @@</span><br><span> PAD_GPI(GPIO_135, PULL_UP),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const static struct soc_amd_gpio gpio_set_stage_ram[] = {</span><br><span> /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */</span><br><span> PAD_NF(GPIO_2, WAKE_L, PULL_UP),</span><br><span> </span><br><span>@@ -486,7 +486,7 @@</span><br><span> };</span><br><span> </span><br><span> const __attribute__((weak))</span><br><span style="color: hsl(0, 100%, 40%);">-struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+struct soc_amd_gpio *variant_early_gpio_table(size_t *size)</span><br><span> {</span><br><span> if (board_id() < 2) {</span><br><span> *size = ARRAY_SIZE(gpio_set_stage_reset_old);</span><br><span>@@ -498,7 +498,7 @@</span><br><span> }</span><br><span> </span><br><span> const __attribute__((weak))</span><br><span style="color: hsl(0, 100%, 40%);">-struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+struct soc_amd_gpio *variant_gpio_table(size_t *size)</span><br><span> {</span><br><span> if (board_id() < 2) {</span><br><span> *size = ARRAY_SIZE(gpio_set_stage_ram_old);</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h</span><br><span>index bc35ff5..fa74b56 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h</span><br><span>@@ -29,8 +29,8 @@</span><br><span> int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len);</span><br><span> int variant_get_xhci_oc_map(uint16_t *usb_oc_map);</span><br><span> int variant_get_ehci_oc_map(uint16_t *usb_oc_map);</span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size);</span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio *variant_gpio_table(size_t *size);</span><br><span> void variant_romstage_entry(int s3_resume);</span><br><span> </span><br><span> #endif /* __BASEBOARD_VARIANTS_H__ */</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c</span><br><span>index 2f40546..a621a58 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> * bootblock while GPIO pins used only by the OS should be initialized at</span><br><span> * ramstage.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio gpio_set_stage_reset[] = {</span><br><span> /* AGPIO2, to become event generator */</span><br><span> { GPIO_2, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT },</span><br><span> </span><br><span>@@ -72,7 +72,7 @@</span><br><span> {GPIO_144, Function1, INPUT }</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio gpio_set_stage_ram[] = {</span><br><span> /* AGPIO 12 */</span><br><span> { GPIO_12, Function2, FCH_GPIO_PULL_UP_ENABLE | INPUT },</span><br><span> </span><br><span>@@ -102,13 +102,13 @@</span><br><span> {GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio *variant_early_gpio_table(size_t *size)</span><br><span> {</span><br><span> *size = ARRAY_SIZE(gpio_set_stage_reset);</span><br><span> return gpio_set_stage_reset;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_gpio *variant_gpio_table(size_t *size)</span><br><span> {</span><br><span> *size = ARRAY_SIZE(gpio_set_stage_ram);</span><br><span> return gpio_set_stage_ram;</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index c0a48b3..5af9a6e 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -352,7 +352,7 @@</span><br><span> #define FCH_AOAC_STAT0 BIT(6)</span><br><span> #define FCH_AOAC_STAT1 BIT(7)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-struct soc_amd_stoneyridge_gpio {</span><br><span style="color: hsl(120, 100%, 40%);">+struct soc_amd_gpio {</span><br><span> uint8_t gpio;</span><br><span> uint8_t function;</span><br><span> uint8_t control;</span><br><span>@@ -449,7 +449,7 @@</span><br><span> *</span><br><span> * @return none</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr,</span><br><span style="color: hsl(120, 100%, 40%);">+void sb_program_gpios(const struct soc_amd_gpio *gpio_ptr,</span><br><span> size_t size);</span><br><span> /**</span><br><span> * @brief Find the size of a particular wide IO</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index a2a54c2..43d6f76 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -172,7 +172,7 @@</span><br><span> return irq_association;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr,</span><br><span style="color: hsl(120, 100%, 40%);">+void sb_program_gpios(const struct soc_amd_gpio *gpio_ptr,</span><br><span> size_t size)</span><br><span> {</span><br><span> void *tmp_ptr;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25726">change 25726</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25726"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543 </div>
<div style="display:none"> Gerrit-Change-Number: 25726 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>