<p>Jonathan Neuschäfer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25684">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Documentation/Intel: Adjust heading levels<br><br>Adjust the headings so that there is only one h1 tag per file.<br><br>Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c<br>Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>M Documentation/Intel/Board/board.html<br>M Documentation/Intel/Board/galileo.html<br>M Documentation/Intel/SoC/quark.html<br>M Documentation/Intel/SoC/soc.html<br>M Documentation/Intel/fsp1_1.html<br>M Documentation/Intel/index.html<br>M Documentation/Intel/vboot.html<br>7 files changed, 72 insertions(+), 70 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/25684/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html</span><br><span>index d09805b..4ba51df 100644</span><br><span>--- a/Documentation/Intel/Board/board.html</span><br><span>+++ b/Documentation/Intel/Board/board.html</span><br><span>@@ -22,7 +22,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="RequiredFiles">Required Files</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="RequiredFiles">Required Files</a></h2></span><br><span> <p></span><br><span> Create the board directory as src/mainboard/<Vendor>/<Board>.</span><br><span> </p></span><br><span>@@ -80,7 +80,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="SerialOutput">Enable Serial Output</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="SerialOutput">Enable Serial Output</a></h2></span><br><span> <p></span><br><span> Use the following steps to enable serial output:</span><br><span> </p></span><br><span>@@ -103,7 +103,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="SpdData">Memory Timing Data</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="SpdData">Memory Timing Data</a></h2></span><br><span> <p></span><br><span> Memory timing data is located in the flash. This data is in the format of</span><br><span> <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a></span><br><span>@@ -183,7 +183,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="DisablePciDevices">Disable PCI Devices</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="DisablePciDevices">Disable PCI Devices</a></h2></span><br><span> <p></span><br><span> Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all</span><br><span> of the devices in the system. Edit the devicetree.cb file:</span><br><span>@@ -209,7 +209,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="AcpiTables">ACPI Tables</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="AcpiTables">ACPI Tables</a></h2></span><br><span> <ol></span><br><span> <li>Edit Kconfig</span><br><span> <ol type="A"></span><br><span>diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html</span><br><span>index cdc8fda..cd0a28a 100644</span><br><span>--- a/Documentation/Intel/Board/galileo.html</span><br><span>+++ b/Documentation/Intel/Board/galileo.html</span><br><span>@@ -26,7 +26,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Galileo Board Documentation</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Galileo Board Documentation</h2></span><br><span> <ul></span><br><span> <li>Common Components</span><br><span> <ul></span><br><span>@@ -46,7 +46,7 @@</span><br><span> <li>Make a bootable <a target="_blank" href="https://software.intel.com/en-us/get-started-galileo-linux-step1">micro SD card</a></li></span><br><span> </ul></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Galileo Gen 2 Board Documentation</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Galileo Gen 2 Board Documentation</h3></span><br><span> <ul></span><br><span> <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg">Block Diagram</a></li></span><br><span> <li><a target="_blank" href="https://software.intel.com/en-us/iot/library/galileo-getting-started">Getting Started</a></li></span><br><span>@@ -70,7 +70,7 @@</span><br><span> </li></span><br><span> </ul></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Galileo Gen 1 Board Documentation</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Galileo Gen 1 Board Documentation</h3></span><br><span> <ul></span><br><span> <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/galileo-g1-datasheet.pdf">Datasheet</a></li></span><br><span> <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g1-schematic.pdf">Schematic</a></li></span><br><span>@@ -89,7 +89,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Debug Tools</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Debug Tools</h2></span><br><span> <ul></span><br><span> <li>Flash Programmer:</span><br><span> <ul></span><br><span>diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html</span><br><span>index 9c180da..c3eead2 100644</span><br><span>--- a/Documentation/Intel/SoC/quark.html</span><br><span>+++ b/Documentation/Intel/SoC/quark.html</span><br><span>@@ -28,7 +28,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Quark™ Documentation</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Quark™ Documentation</h2></span><br><span> <ul></span><br><span> <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png">Block Diagram</a></li></span><br><span> <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/quark/specifications.html">Specifications</a>:</span><br><span>@@ -49,7 +49,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="CorebootPayloadPkg">Quark™ EDK2 CorebootPayloadPkg</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="CorebootPayloadPkg">Quark™ EDK2 CorebootPayloadPkg</a></h2></span><br><span> <p></span><br><span> Build Instructions:</span><br><span> </p></span><br><span>@@ -81,7 +81,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="BuildEnvironment">Quark™ EDK2 Build Environment</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="BuildEnvironment">Quark™ EDK2 Build Environment</a></h2></span><br><span> <p></span><br><span> Use the following steps to setup a build environment:</span><br><span> </p></span><br><span>@@ -118,7 +118,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="QuarkFsp">Quark™ FSP</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="QuarkFsp">Quark™ FSP</a></h2></span><br><span> <p></span><br><span> Getting the Quark FSP source:</span><br><span> </p></span><br><span>@@ -130,7 +130,7 @@</span><br><span> <li>Use git to clone <a target="_blank" href="https://review.gerrithub.io/#/admin/projects/LeeLeahy/quarkfsp">QuarkFspPkg</a> into the QuarkFpsPkg directory (.)</li></span><br><span> </ol></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Building QuarkFspPkg</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Building QuarkFspPkg</h3></span><br><span> <p></span><br><span> There are two versions of FSP: FSP 1.1 and FSP 2.0. There are also two</span><br><span> different implementations of FSP, one using subroutines without SEC and</span><br><span>@@ -157,7 +157,7 @@</span><br><span> </li></span><br><span> </ul></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Copying FSP files into coreboot Source Tree</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Copying FSP files into coreboot Source Tree</h3></span><br><span> <p></span><br><span> There are some helper scripts to copy the FSP output into the coreboot</span><br><span> source tree. The parameters to these scripts are:</span><br><span>@@ -182,7 +182,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Quark™ EDK2 BIOS</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Quark™ EDK2 BIOS</h2></span><br><span> <p></span><br><span> Build Instructions:</span><br><span> </p></span><br><span>diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html</span><br><span>index 147b0a1..d91166f 100644</span><br><span>--- a/Documentation/Intel/SoC/soc.html</span><br><span>+++ b/Documentation/Intel/SoC/soc.html</span><br><span>@@ -39,7 +39,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="RequiredFiles">Required Files</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="RequiredFiles">Required Files</a></h2></span><br><span> <p></span><br><span> Create the directory as src/soc/<Vendor>/<Chip Family>.</span><br><span> </p></span><br><span>@@ -69,13 +69,13 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="Descriptor">Start Booting</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="Descriptor">Start Booting</a></h2></span><br><span> <p></span><br><span> Some SoC parts require additional firmware components in the flash.</span><br><span> This section describes how to add those pieces.</span><br><span> </p></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Intel Firmware Descriptor</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Intel Firmware Descriptor</h3></span><br><span> <p></span><br><span> The Intel Firmware Descriptor (IFD) is located at the base of the flash part.</span><br><span> The following command overwrites the base of the flash image with the Intel</span><br><span>@@ -84,7 +84,7 @@</span><br><span> <pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre></span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2><a name="MEB">Management Engine Binary</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3><a name="MEB">Management Engine Binary</a></h3></span><br><span> <p></span><br><span> Some SoC parts contain and require that the Management Engine (ME) be running</span><br><span> before it is possible to bring the x86 processor out of reset. A binary file</span><br><span>@@ -96,14 +96,14 @@</span><br><span> </code></pre></span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2><a name="EarlyDebug">Early Debug</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3><a name="EarlyDebug">Early Debug</a></h3></span><br><span> <p></span><br><span> Early debugging between the reset vector and the time the serial port is enabled</span><br><span> is most easily done by writing values to port 0x80.</span><br><span> </p></span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Success</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Success</h3></span><br><span> <p></span><br><span> When the reset vector is successfully invoked, port 0x80 will output the following value:</span><br><span> </p></span><br><span>@@ -118,7 +118,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="Bootblock">Bootblock</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="Bootblock">Bootblock</a></h2></span><br><span> <p></span><br><span> Implement the bootblock using the following steps:</span><br><span> </p></span><br><span>@@ -213,7 +213,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="TempRamInit">TempRamInit</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="TempRamInit">TempRamInit</a></h2></span><br><span> <p></span><br><span> Enable the call to TempRamInit in two stages:</span><br><span> </p></span><br><span>@@ -223,7 +223,7 @@</span><br><span> </ol></span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Find FSP Binary</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Find FSP Binary</h3></span><br><span> <p></span><br><span> Use the following steps to locate the FSP binary:</span><br><span> </p></span><br><span>@@ -267,7 +267,7 @@</span><br><span> </ol></span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Calling TempRamInit</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Calling TempRamInit</h3></span><br><span> <p></span><br><span> Use the following steps to debug the call to TempRamInit:</span><br><span> </p></span><br><span>@@ -301,9 +301,9 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="Romstage">Romstage</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="Romstage">Romstage</a></h2></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2><a name="SerialOutput">Serial Output</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3><a name="SerialOutput">Serial Output</a></h3></span><br><span> <p></span><br><span> The following steps add the serial output support for romstage:</span><br><span> </p></span><br><span>@@ -339,7 +339,7 @@</span><br><span> </ol></span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2><a name="PreviousSleepState">Determine Previous Sleep State</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3><a name="PreviousSleepState">Determine Previous Sleep State</a></h3></span><br><span> <p></span><br><span> The following steps implement the code to get the previous sleep state:</span><br><span> </p></span><br><span>@@ -362,7 +362,7 @@</span><br><span> </ol></span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2><a name="MemoryInit">MemoryInit Support</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3><a name="MemoryInit">MemoryInit Support</a></h3></span><br><span> <p></span><br><span> The following steps implement the code to support the FSP MemoryInit call:</span><br><span> </p></span><br><span>@@ -390,7 +390,7 @@</span><br><span> </ol></span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2><a name="DisableShadowRom">Disable Shadow ROM</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3><a name="DisableShadowRom">Disable Shadow ROM</a></h3></span><br><span> <p></span><br><span> A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff.</span><br><span> This shadow needs to be disabled to allow RAM to properly respond to</span><br><span>@@ -402,9 +402,9 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="Ramstage">Ramstage</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="Ramstage">Ramstage</a></h2></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2><a name="DeviceTree">Start Device Tree Processing</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3><a name="DeviceTree">Start Device Tree Processing</a></h3></span><br><span> <p></span><br><span> The src/mainboard/<Vendor>/<Board>/devicetree.cb file drives the</span><br><span> execution during ramstage. This file is processed by the util/sconfig utility</span><br><span>@@ -417,7 +417,7 @@</span><br><span> state of the state machine.</span><br><span> </p></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h3><a name="ChipOperations">Chip Operations</a></h3></span><br><span style="color: hsl(120, 100%, 40%);">+<h4><a name="ChipOperations">Chip Operations</a></h4></span><br><span> <p></span><br><span> Kick-starting the ramstage state machine requires creating the operation table</span><br><span> for the chip listed in devicetree.cb:</span><br><span>@@ -437,7 +437,7 @@</span><br><span> <li>Edit src/soc/<SoC Vendor>/<SoC Family>/Makefile.inc and add chip.c to ramstage</li></span><br><span> </ol></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h3>Domain Operations</h3></span><br><span style="color: hsl(120, 100%, 40%);">+<h4>Domain Operations</h4></span><br><span> <p></span><br><span> coreboot uses the domain operation table to initiate operations on all of the</span><br><span> devices in the domain. By default coreboot enables all PCI devices which it</span><br><span>@@ -482,7 +482,7 @@</span><br><span> </ol></span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2><a name="DeviceDrivers">PCI Device Drivers</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3><a name="DeviceDrivers">PCI Device Drivers</a></h3></span><br><span> <p></span><br><span> PCI device drivers consist of a ".c" file which contains a "pci_driver" data</span><br><span> structure at the end of the file with the attribute tag "__pci_driver". This</span><br><span>@@ -509,7 +509,7 @@</span><br><span> </li></span><br><span> </ol></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h3><a name="SubsystemIds">Subsystem IDs</a></h3></span><br><span style="color: hsl(120, 100%, 40%);">+<h4><a name="SubsystemIds">Subsystem IDs</a></h4></span><br><span> <p></span><br><span> PCI subsystem IDs are assigned during the BS_DEV_ENABLE state. The device</span><br><span> driver may use the common mechanism to assign subsystem IDs by adding</span><br><span>@@ -534,7 +534,7 @@</span><br><span> </span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Set up the <a name="MemoryMap">Memory Map</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Set up the <a name="MemoryMap">Memory Map</a></h3></span><br><span> <p></span><br><span> The memory map is built by the various PCI device drivers during the</span><br><span> BS_DEV_RESOURCES state of ramstage. The northcluster driver will typically</span><br><span>@@ -571,12 +571,12 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="AcpiTables">ACPI Tables</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="AcpiTables">ACPI Tables</a></h2></span><br><span> <p></span><br><span> One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>.</span><br><span> </p></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>FADT</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>FADT</h3></span><br><span> <p></span><br><span> The EDK2 module</span><br><span> CorebootModulePkg/Library/CbParseLib/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbParseLib/CbParseLib.c#l450">CbParseLib.c</a></span><br><span>@@ -679,7 +679,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="LegacyHardware">Legacy Hardware</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="LegacyHardware">Legacy Hardware</a></h2></span><br><span> <p></span><br><span> One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>.</span><br><span> </p></span><br><span>@@ -731,4 +731,4 @@</span><br><span> <hr></span><br><span> <p>Modified: 4 March 2016</p></span><br><span> </body></span><br><span style="color: hsl(0, 100%, 40%);">-</html></span><br><span>\ No newline at end of file</span><br><span style="color: hsl(120, 100%, 40%);">+</html></span><br><span>diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html</span><br><span>index 1e1e88f..94cb6bf 100644</span><br><span>--- a/Documentation/Intel/fsp1_1.html</span><br><span>+++ b/Documentation/Intel/fsp1_1.html</span><br><span>@@ -5,7 +5,9 @@</span><br><span> </head></span><br><span> <body></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h1>x86 FSP 1.1 Integration</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h1>FSP 1.1</h1></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+<h2>x86 FSP 1.1 Integration</h2></span><br><span> <p></span><br><span> Firmware Support Package (FSP) integration requires System-on-a-Chip (SoC)</span><br><span> and board support. The combined steps are listed</span><br><span>@@ -26,8 +28,8 @@</span><br><span> </ul></span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="RequiredFiles">Required Files</a></h1></span><br><span style="color: hsl(0, 100%, 40%);">-<h2><a name="corebootRequiredFiles">coreboot Required Files</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="RequiredFiles">Required Files</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3><a name="corebootRequiredFiles">coreboot Required Files</a></h3></span><br><span> <ol></span><br><span> <li>Create the following directories if they do not already exist:</span><br><span> <ul></span><br><span>@@ -47,7 +49,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h2></span><br><span> <p></span><br><span> Add the FSP binary to the coreboot flash image using the following command:</span><br><span> </p></span><br><span>@@ -59,7 +61,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h2></span><br><span> <p></span><br><span> Set the following Kconfig values:</span><br><span> </p></span><br><span>diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html</span><br><span>index b2e826d..b4daa96 100644</span><br><span>--- a/Documentation/Intel/index.html</span><br><span>+++ b/Documentation/Intel/index.html</span><br><span>@@ -5,15 +5,15 @@</span><br><span> </head></span><br><span> <body></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Intel® x86 Boards</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h1>Intel® x86</h1></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Intel® x86 Boards</h2></span><br><span> <ul></span><br><span> <li><a target="_blank" href="Board/galileo.html">Galileo</a></li></span><br><span> <li><a target="_blank" href="http://wiki.minnowboard.org/Coreboot">MinnowBoard MAX</a></li></span><br><span> </ul></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Intel® x86 SoCs</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Intel® x86 SoCs</h2></span><br><span> <ul></span><br><span> <li><a target="_blank" href="SoC/quark.html">Quark™</a></li></span><br><span> </ul></span><br><span>@@ -21,7 +21,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>x86 coreboot Development</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>x86 coreboot Development</h2></span><br><span> <ul></span><br><span> <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li></span><br><span> <li><a target="_blank" href="development.html">Overall</a> development</li></span><br><span>@@ -35,7 +35,7 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Payload Development</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Payload Development</h2></span><br><span> <ul></span><br><span> <li><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a></span><br><span> <ul></span><br><span>@@ -50,13 +50,13 @@</span><br><span> </span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1><a name="Documentation">Documentation</a></h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2><a name="Documentation">Documentation</a></h2></span><br><span> <ul></span><br><span> <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf">Software Developer Manual</a></li></span><br><span> <li><a target="_blank" href="http://www.uefi.org/specifications">UEFI Specifications</a></li></span><br><span> </ul></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2><a name="Edk2Documentation">EDK-II Documentation</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3><a name="Edk2Documentation">EDK-II Documentation</a></h3></span><br><span> <ul></span><br><span> <li>Build <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/Build_Spec_1_26.pdf">V1.26</a></li></span><br><span> <li>Coding Standards <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf">V2.1</a></li></span><br><span>@@ -71,14 +71,14 @@</span><br><span> <li>VRF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/VFR_1_9.pdf">V1.9</a></li></span><br><span> </ul></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2><a name="FspDocumentation">FSP Documentation</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3><a name="FspDocumentation">FSP Documentation</a></h3></span><br><span> <ul></span><br><span> <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf">V2.0</a></li></span><br><span> <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li></span><br><span> <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf">V1.0</a></li></span><br><span> </ul></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2><a name="FeatureDocumentation">Feature Documentation</a></h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3><a name="FeatureDocumentation">Feature Documentation</a></h3></span><br><span> <table border="1"></span><br><span> <tr bgcolor="#c0ffc0"><th>Feature/Specification</th><th>Linux View/Test</th><th>EDK-II View/Test</th></tr></span><br><span> <tr></span><br><span>diff --git a/Documentation/Intel/vboot.html b/Documentation/Intel/vboot.html</span><br><span>index 3a92989..ca49ac2 100644</span><br><span>--- a/Documentation/Intel/vboot.html</span><br><span>+++ b/Documentation/Intel/vboot.html</span><br><span>@@ -24,7 +24,7 @@</span><br><span> within the TPM.</span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Root of Trust</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Root of Trust</h2></span><br><span> <p></span><br><span> When using vboot, the root-of-trust is basically the read-only portion of the</span><br><span> SPI flash. The following items factor into the trust equation:</span><br><span>@@ -57,7 +57,7 @@</span><br><span> </p></span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Firmware Layout</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Firmware Layout</h2></span><br><span> <p></span><br><span> Several sections are added to the firmware layout to support vboot:</span><br><span> </p></span><br><span>@@ -71,7 +71,7 @@</span><br><span> The following sections describe the various portions of the flash layout.</span><br><span> </p></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Read-Only Section</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Read-Only Section</h3></span><br><span> <p></span><br><span> The read-only section contains a coreboot file system (CBFS) that contains all</span><br><span> of the boot firmware necessary to perform recovery for the system. This</span><br><span>@@ -87,14 +87,14 @@</span><br><span> <li>coreboot file system containing read-only recovery firmware</li></span><br><span> </ul></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Google Binary Blob (GBB) Area</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Google Binary Blob (GBB) Area</h3></span><br><span> <p></span><br><span> The GBB area is part of the read-only section. This area contains a 4096 or</span><br><span> 8192 bit public root RSA key that is used to verify the VBLOCK area to obtain</span><br><span> the firmware signing key.</span><br><span> </p></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Recovery Firmware</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Recovery Firmware</h3></span><br><span> <p></span><br><span> The recovery firmware is contained within a coreboot file system and consists</span><br><span> of:</span><br><span>@@ -129,7 +129,7 @@</span><br><span> </p></span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Read/Write Section</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Read/Write Section</h3></span><br><span> </span><br><span> <p></span><br><span> The read/write sections contain an area which contains the firmware signing</span><br><span>@@ -158,7 +158,7 @@</span><br><span> </p></span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Firmware Updates</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Firmware Updates</h2></span><br><span> <p></span><br><span> The read/write sections exist in one of three states:</span><br><span> </p></span><br><span>@@ -208,7 +208,7 @@</span><br><span> </p></span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Build Flags</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Build Flags</h2></span><br><span> <p></span><br><span> The following Kconfig values need to be selected to enable vboot:</span><br><span> </p></span><br><span>@@ -255,7 +255,7 @@</span><br><span> </p></span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Signing the coreboot Image</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Signing the coreboot Image</h2></span><br><span> <p></span><br><span> The following command script is an example of how to sign the coreboot image file.</span><br><span> This script is used on the Intel Galileo board and creates the GBB area and</span><br><span>@@ -341,7 +341,7 @@</span><br><span> </code></pre></span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Boot Flow</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Boot Flow</h2></span><br><span> <p></span><br><span> The reset vector exist in the read-only area and points to the bootblock entry</span><br><span> point. The only copy of the bootblock exists in the read-only area of the SPI</span><br><span>@@ -367,7 +367,7 @@</span><br><span> </p></span><br><span> </span><br><span> <hr></span><br><span style="color: hsl(0, 100%, 40%);">-<h1>Chromebook Special Features</h1></span><br><span style="color: hsl(120, 100%, 40%);">+<h2>Chromebook Special Features</h2></span><br><span> <p></span><br><span> Google's Chromebooks have some special features:</span><br><span> </p></span><br><span>@@ -376,7 +376,7 @@</span><br><span> <li>Write-protect screw</li></span><br><span> </ul></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Developer Mode</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Developer Mode</h3></span><br><span> <p></span><br><span> Developer mode allows the user to use coreboot to boot another operating system.</span><br><span> This may be a another (beta) version of Chrome OS, or another flavor of</span><br><span>@@ -386,7 +386,7 @@</span><br><span> security to access files on the local system or cloud.</span><br><span> </p></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-<h2>Write Protect Screw</h2></span><br><span style="color: hsl(120, 100%, 40%);">+<h3>Write Protect Screw</h3></span><br><span> <p></span><br><span> Chromebooks have a write-protect screw which provides the ground to the</span><br><span> write-protect pin of the SPI flash. Google specifically did this to allow</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25684">change 25684</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25684"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c </div>
<div style="display:none"> Gerrit-Change-Number: 25684 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>