<p><a href="https://review.coreboot.org/25663">View Change</a></p><p>5 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c">File src/device/dram/ddr3.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c@298">Patch Set #1, Line 298:</a> <code style="font-family:monospace,monospace">     /* Minimum CAS Write Latency Time (tCWLmin) - not present in standard SPD */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">over line</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c@491">Patch Set #1, Line 491:</a> <code style="font-family:monospace,monospace">      dimm->cas_supported = (xmp[4] << 8) + xmp[3];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">According to spec 1.1 it's <br>((xmp[4] << 8) + xmp[3]) & 0x7fff</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c@515">Patch Set #1, Line 515:</a> <code style="font-family:monospace,monospace"> dimm->tCWL = xmp[5] * mtb;;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Remove second semicolon</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c@516">Patch Set #1, Line 516:</a> <code style="font-family:monospace,monospace">      /* Minimum CMD rate */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">"System CMD Rate Mode"</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/25663/1/src/include/device/dram/ddr3.h">File src/include/device/dram/ddr3.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/25663/1/src/include/device/dram/ddr3.h@166">Patch Set #1, Line 166:</a> <code style="font-family:monospace,monospace">        u32 tCMD;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">u16 should be sufficient</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/25663">change 25663</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25663"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
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<div style="display:none"> Gerrit-Change-Id: Ie4f545ed1df92c146be02f56fea0ca9037478649 </div>
<div style="display:none"> Gerrit-Change-Number: 25663 </div>
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<div style="display:none"> Gerrit-Owner: Dan Elkouby <streetwalkermc@gmail.com> </div>
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<div style="display:none"> Gerrit-CC: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Comment-Date: Sat, 14 Apr 2018 09:30:46 +0000 </div>
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