<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25658">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/lpc.c: Fix bit definitions<br><br>The latest public BKDG releases some previously undefined (reserved) bits,<br>also some bits were wrongly named (possibly copied from previous chip).<br>Fix these definitions, including header file where they are defined.<br><br>BUG=b:77940747<br>TEST=Build and boot grunt.<br><br>Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/lpc.c<br>2 files changed, 17 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/25658/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index bdcb38f..c0a48b3 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -107,6 +107,9 @@</span><br><span> #define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))</span><br><span> </span><br><span> #define LPC_PCI_CONTROL 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define IMC_PRESENT BIT(7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define IMC_TO_HOST_SEMAPHORE BIT(6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HOST_TO_IMC_SEMAPHORE BIT(5)</span><br><span> #define LEGACY_DMA_EN BIT(2)</span><br><span> </span><br><span> #define LPC_IO_PORT_DECODE_ENABLE 0x44</span><br><span>@@ -149,12 +152,17 @@</span><br><span> #define DECODE_IO_PORT_ENABLE6 BIT(23)</span><br><span> #define DECODE_IO_PORT_ENABLE5 BIT(22)</span><br><span> #define DECODE_IO_PORT_ENABLE4 BIT(21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_MEM_PORT_ENABLE1 BIT(20)</span><br><span> #define DECODE_IO_PORT_ENABLE3 BIT(19)</span><br><span> #define DECODE_IO_PORT_ENABLE2 BIT(18)</span><br><span> #define DECODE_IO_PORT_ENABLE1 BIT(17)</span><br><span> #define DECODE_IO_PORT_ENABLE0 BIT(16)</span><br><span> #define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DECODE_RTC_IO_ENABLE BIT(6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_MEM_PORT_ENABLE0 BIT(5)</span><br><span> #define LPC_WIDEIO0_ENABLE BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ALTERNATE_SIO_ENABLE BIT(1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_SIO_ENABLE BIT(0)</span><br><span> /* Assuming word access to higher word (register 0x4a) */</span><br><span> #define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a</span><br><span> #define LPC_WIDEIO2_ENABLE_H BIT(9)</span><br><span>@@ -167,6 +175,9 @@</span><br><span> #define DECODE_IO_PORT_ENABLE1_H BIT(1)</span><br><span> #define DECODE_IO_PORT_ENABLE0_H BIT(0)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_MEM_PORT1 0x4c</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_MEM_PORT0 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * Register 0x64 is 32-bit, composed by two 16-bit sub-registers.</span><br><span> * For ease of access, each sub-register is declared separetely.</span><br><span>@@ -200,7 +211,8 @@</span><br><span> #define LPC_ROM_DMA_EC_HOST_CONTROL 0xb8</span><br><span> </span><br><span> #define LPC_HOST_CONTROL 0xbb</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_FROM_HOST_PREFETCH_EN BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define IMC_PAGE_FROM_HOST_EN BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define IMC_PORT_FROM_HOST_EN BIT(3)</span><br><span> </span><br><span> /* SPI Controller */</span><br><span> #define SPI_CNTRL0 0x00</span><br><span>diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c</span><br><span>index 10f4a4b..eb51281 100644</span><br><span>--- a/src/soc/amd/stoneyridge/lpc.c</span><br><span>+++ b/src/soc/amd/stoneyridge/lpc.c</span><br><span>@@ -76,11 +76,12 @@</span><br><span> pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte);</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12.</span><br><span style="color: hsl(0, 100%, 40%);">- * todo: verify against BKDG</span><br><span style="color: hsl(120, 100%, 40%);">+ * IMC is not used, but some of its registers and ports need to be</span><br><span style="color: hsl(120, 100%, 40%);">+ * programmed/accessed. So enable CPU access to them. This fixes</span><br><span style="color: hsl(120, 100%, 40%);">+ * SPI_CS# timing issue when running at 66MHz.</span><br><span> */</span><br><span> byte = pci_read_config8(dev, LPC_HOST_CONTROL);</span><br><span style="color: hsl(0, 100%, 40%);">- byte |= SPI_FROM_HOST_PREFETCH_EN | 1 << 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ byte |= IMC_PAGE_FROM_HOST_EN | IMC_PORT_FROM_HOST_EN;</span><br><span> pci_write_config8(dev, LPC_HOST_CONTROL, byte);</span><br><span> </span><br><span> cmos_check_update_date();</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25658">change 25658</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f </div>
<div style="display:none"> Gerrit-Change-Number: 25658 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>