<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25657">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Assign Cpu Mp PPI FSP upd to handle feature programming<br><br>BRANCH=none<br>BUG=b:74436746<br>TEST=Able to make call between FSP to Coreboot.<br><br>Change-Id: Iae1984cfd81cbaecf24bb82229e48b9f36abd110<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/chip.c<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>3 files changed, 32 insertions(+), 26 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/25657/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index 541e516..071d703 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -60,6 +60,7 @@</span><br><span> select SOC_INTEL_COMMON_BLOCK_P2SB</span><br><span> select SOC_INTEL_COMMON_BLOCK_PCR</span><br><span> select SOC_INTEL_COMMON_BLOCK_PMC</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_PUBLISH_MP_SERVICES_PPI</span><br><span> select SOC_INTEL_COMMON_BLOCK_RTC</span><br><span> select SOC_INTEL_COMMON_BLOCK_SA</span><br><span> select SOC_INTEL_COMMON_BLOCK_SATA</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index 5fc3a55..371b4ef 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -19,6 +19,11 @@</span><br><span> #include <device/pci.h></span><br><span> #include <fsp/api.h></span><br><span> #include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_PUBLISH_MP_SERVICES_PPI)</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/mp_service_ppi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/cpulib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> #include <intelblocks/xdci.h></span><br><span> #include <romstage_handoff.h></span><br><span> #include <soc/intel/common/vbt.h></span><br><span>@@ -200,6 +205,10 @@</span><br><span> params->Usb3OverCurrentPin[i] = 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_PUBLISH_MP_SERVICES_PPI)</span><br><span style="color: hsl(120, 100%, 40%);">+ params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> mainboard_silicon_init_params(params);</span><br><span> </span><br><span> /* Unlock upper 8 bytes of RTC RAM */</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>index 4daf891..14fa8cd 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>@@ -1093,22 +1093,25 @@</span><br><span> **/</span><br><span> UINT16 ImonSlope1[5];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0324 - CPU VR Power Delivery Design</span><br><span style="color: hsl(0, 100%, 40%);">- Used to communicate the power delivery design capability of the board. This value</span><br><span style="color: hsl(0, 100%, 40%);">- is an enum of the available power delivery segments that are defined in the Platform</span><br><span style="color: hsl(0, 100%, 40%);">- Design Guide.</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0324 - CpuMpPpi</span><br><span style="color: hsl(120, 100%, 40%);">+ Pointer for CpuMpPpi</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 VrPowerDeliveryDesign;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 CpuMpPpi;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0328 - ReservedCpuPostMemProduction</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0328 - CpuInitMpLibHob</span><br><span style="color: hsl(120, 100%, 40%);">+ Pointer for CpuInitMpLibHob</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 CpuInitMpLibHob;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x032C - ReservedCpuPostMemProduction</span><br><span> Reserved for CPU Post-Mem Production</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 ReservedCpuPostMemProduction[1];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0329</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x032D</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace10[29];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace10[25];</span><br><span> </span><br><span> /** Offset 0x0346 - Enable DMI ASPM</span><br><span> Deprecated.</span><br><span>@@ -1876,6 +1879,7 @@</span><br><span> 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5</span><br><span> pads termination respectively. One byte for each controller, byte0 for I2C0, byte1</span><br><span> for I2C1, and so on.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU</span><br><span> **/</span><br><span> UINT8 PchSerialIoI2cPadsTermination[6];</span><br><span> </span><br><span>@@ -2154,17 +2158,9 @@</span><br><span> **/</span><br><span> UINT8 SataRstCpuAttachedStorage;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0752 - Enable 8254 Static Clock Gating On S3</span><br><span style="color: hsl(0, 100%, 40%);">- This is only applicable when Enable8254ClockGating is disabled. FSP will do the</span><br><span style="color: hsl(0, 100%, 40%);">- 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This</span><br><span style="color: hsl(0, 100%, 40%);">- avoids the SMI requirement for the programming.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0752</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Enable8254ClockGatingOnS3;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0753</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace25;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace25[2];</span><br><span> </span><br><span> /** Offset 0x0754 - Pch PCIE device override table pointer</span><br><span> The PCIe device table is being used to override PCIe device ASPM settings. This</span><br><span>@@ -2297,7 +2293,7 @@</span><br><span> **/</span><br><span> UINT8 ChapDeviceEnable;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07B2 - Skip PAM register lock</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B2 - Skip PAM regsiter lock</span><br><span> Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):</span><br><span> PAM registers will be locked by RC</span><br><span> $EN_DIS</span><br><span>@@ -2480,7 +2476,7 @@</span><br><span> </span><br><span> /** Offset 0x07DA - Tcc Offset Lock</span><br><span> Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature</span><br><span style="color: hsl(0, 100%, 40%);">- target; <b>0: Disabled</b>; 1: Enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ target; 0: Disabled; <b>1: Enabled </b>.</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 TccOffsetLock;</span><br><span>@@ -2844,10 +2840,9 @@</span><br><span> **/</span><br><span> UINT16 PsysPmax;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0</span><br><span style="color: hsl(0, 100%, 40%);">- Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0858</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 CstateLatencyControl0Irtl;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Reserved0[2];</span><br><span> </span><br><span> /** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1</span><br><span> Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF</span><br><span>@@ -2894,13 +2889,13 @@</span><br><span> </span><br><span> /** Offset 0x0870 - Package PL4 power limit</span><br><span> Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 1023875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125</span><br><span> **/</span><br><span> UINT32 PowerLimit4;</span><br><span> </span><br><span> /** Offset 0x0874 - Tcc Offset Time Window for RATL</span><br><span> Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 1023875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125</span><br><span> **/</span><br><span> UINT32 TccOffsetTimeWindowForRatl;</span><br><span> </span><br><span>@@ -3089,7 +3084,8 @@</span><br><span> UINT8 PchUnlockGpioPads;</span><br><span> </span><br><span> /** Offset 0x08C2 - PCH Unlock SBI access</span><br><span style="color: hsl(0, 100%, 40%);">- Deprecated</span><br><span style="color: hsl(120, 100%, 40%);">+ This unlock the SBI lock bit to allow SBI after post time. 0: Lock SBI access; 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ Unlock SBI access.</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 PchSbiUnlock;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25657">change 25657</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25657"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iae1984cfd81cbaecf24bb82229e48b9f36abd110 </div>
<div style="display:none"> Gerrit-Change-Number: 25657 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>