<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25668">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Force LPC IO decode settings<br><br>Force PCH LPC generic IO ranges are identical between PCH LPC pci config<br>space and DMI PCR registers. Reference documentation from 570374 chapter<br>2.4.1.<br><br>Bug=77944335<br>TEST=Boot up in OS in meowth board, using iotools to read LPC pci<br>config space offset 0x84~0x90 and compare with values read from DMI PCR<br>private register offset 0x2730~0x273c are identical.<br><br>Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/lpc.c<br>1 file changed, 15 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/25668/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c</span><br><span>index c02d66e..9d3488a 100644</span><br><span>--- a/src/soc/intel/cannonlake/lpc.c</span><br><span>+++ b/src/soc/intel/cannonlake/lpc.c</span><br><span>@@ -30,6 +30,7 @@</span><br><span> #include <intelblocks/pcr.h></span><br><span> #include <reg_script.h></span><br><span> #include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/lpc.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pcr_ids.h></span><br><span> </span><br><span>@@ -68,6 +69,19 @@</span><br><span> }</span><br><span> </span><br><span> #if ENV_RAMSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_mirror_dmi_pcr_io_dec(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Mirror these same settings in DMI PCR */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC));</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC));</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC));</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void pch_enable_ioapic(const struct device *dev)</span><br><span> {</span><br><span> u32 reg32;</span><br><span>@@ -202,6 +216,7 @@</span><br><span> setup_i8259();</span><br><span> i8259_configure_irq_trigger(9, 1);</span><br><span> clock_gate_8254(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_mirror_dmi_pcr_io_dec();</span><br><span> }</span><br><span> </span><br><span> /* Fill up LPC IO resource structure inside SoC directory */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25668">change 25668</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25668"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca </div>
<div style="display:none"> Gerrit-Change-Number: 25668 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>