<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25665">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/southbridge.c: Fix bit definitions<br><br>The latest public BKDG releases some previously undefined (reserved) bits.<br>Fix these definitions, including header file where they are defined.<br><br>BUG=b:77940747<br>TEST=Build and boot grunt.<br><br>Change-Id: Icb5334110248d7806421200a161fa3befefcea8a<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>M src/soc/amd/stoneyridge/northbridge.c<br>2 files changed, 7 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/25665/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>index 92bce98..365a9f5 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>@@ -20,6 +20,10 @@</span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* D1F1 - HDA Configuration Registers */</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDA_DEV_CTRL_STATUS      0x60</span><br><span style="color: hsl(120, 100%, 40%);">+#define   HDA_NO_SNOOP_EN BIT(11)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* D18F0 - HT Configuration Registers */</span><br><span> #define D18F0_NODE_ID          0x60</span><br><span> #define D18F0_CPU_CNT           0x62 /* BKDG defines as a field in DWORD 0x60 */</span><br><span>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>index a7c78e6..2cefb91 100644</span><br><span>--- a/src/soc/amd/stoneyridge/northbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>@@ -363,9 +363,9 @@</span><br><span> </span><br><span>  /* disable No Snoop */</span><br><span>       dev = dev_find_slot(0, HDA0_DEVFN);</span><br><span style="color: hsl(0, 100%, 40%);">-     value = pci_read_config32(dev, 0x60);</span><br><span style="color: hsl(0, 100%, 40%);">-   value &= ~(1 << 11);</span><br><span style="color: hsl(0, 100%, 40%);">-  pci_write_config32(dev, 0x60, value);</span><br><span style="color: hsl(120, 100%, 40%);">+ value = pci_read_config32(dev, HDA_DEV_CTRL_STATUS);</span><br><span style="color: hsl(120, 100%, 40%);">+  value &= ~HDA_NO_SNOOP_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+        pci_write_config32(dev, HDA_DEV_CTRL_STATUS, value);</span><br><span> }</span><br><span> </span><br><span> void domain_read_resources(device_t dev)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25665">change 25665</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25665"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icb5334110248d7806421200a161fa3befefcea8a </div>
<div style="display:none"> Gerrit-Change-Number: 25665 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>