<p>AndiR has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25659">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/asus/p5qpl-am: Add support for ASUS P5QPL-AM<br><br>Adding support for https://www.asus.com/Motherboards/P5QPLAM/<br><br>The board have a Intel G41 chipset and a Winbond W83627DHG SuperIO.<br>Code is been taken from the Asrock G41C-GS Rev 1 from https://review.coreboot.org/#/c/coreboot/+/21292/<br><br>The only required change was a new gpio.c file.<br><br>Tested and working:<br>PS2, USB, Sound, CPU, GPU, RAM(both dimms) - on Linux 4.14<br><br>Change-Id: I160f9201e812f44ef9842caef851750fb7690c9e<br>---<br>A src/mainboard/asus/p5qpl-am/Kconfig<br>A src/mainboard/asus/p5qpl-am/Kconfig.name<br>A src/mainboard/asus/p5qpl-am/Makefile.inc<br>A src/mainboard/asus/p5qpl-am/acpi/ec.asl<br>A src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl<br>A src/mainboard/asus/p5qpl-am/acpi/platform.asl<br>A src/mainboard/asus/p5qpl-am/acpi/superio.asl<br>A src/mainboard/asus/p5qpl-am/acpi/x4x_pci_irqs.asl<br>A src/mainboard/asus/p5qpl-am/acpi_tables.c<br>A src/mainboard/asus/p5qpl-am/board_info.txt<br>A src/mainboard/asus/p5qpl-am/cmos.default<br>A src/mainboard/asus/p5qpl-am/cmos.layout<br>A src/mainboard/asus/p5qpl-am/cstates.c<br>A src/mainboard/asus/p5qpl-am/devicetree.cb<br>A src/mainboard/asus/p5qpl-am/dsdt.asl<br>A src/mainboard/asus/p5qpl-am/gpio.c<br>A src/mainboard/asus/p5qpl-am/hda_verb.c<br>A src/mainboard/asus/p5qpl-am/romstage.c<br>18 files changed, 868 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/25659/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/asus/p5qpl-am/Kconfig b/src/mainboard/asus/p5qpl-am/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..e69a773</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/Kconfig</span><br><span>@@ -0,0 +1,54 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_ASUS_P5QPL_AM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select ARCH_X86</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_INTEL_SOCKET_LGA775</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_INTEL_X4X</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_I82801GX</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_WINBOND_W83627DHG</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_1024</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_EDID</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_NATIVE_VGA_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select PCIEXP_ASPM</span><br><span style="color: hsl(120, 100%, 40%);">+ select PCIEXP_CLK_PM</span><br><span style="color: hsl(120, 100%, 40%);">+ select PCIEXP_L1_SUB_STATE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_CK505</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "asus/p5qpl-am"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "P5QPL-AM"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "p5qpl-am/devicetree.cb"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_ASUS_P5QPL_AM</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/Kconfig.name b/src/mainboard/asus/p5qpl-am/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..7a101b9</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/Kconfig.name</span><br><span>@@ -0,0 +1,3 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_ASUS_P5QPL_AM</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "P5QPL-AM"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/Makefile.inc b/src/mainboard/asus/p5qpl-am/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..f3d7e76</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/Makefile.inc</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += cstates.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/acpi/ec.asl b/src/mainboard/asus/p5qpl-am/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..2997587</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/acpi/ec.asl</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/* dummy */</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..bb8745e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl</span><br><span>@@ -0,0 +1,53 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This is board specific information:</span><br><span style="color: hsl(120, 100%, 40%);">+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI1 SLOT 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 0, 0, 0x16},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 1, 0, 0x17},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 2, 0, 0x14},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 3, 0, 0x15},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI1 SLOT 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 0, 0, 0x17},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 1, 0, 0x14},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 2, 0, 0x15},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 3, 0, 0x16},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* device not in lspci but in vendor DSDT */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Package() { 0x0008ffff, 0, 0, 0x14}, */</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+} Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* device not in lspci but in vendor DSDT */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, */</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/acpi/platform.asl b/src/mainboard/asus/p5qpl-am/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..6c92a4e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/acpi/platform.asl</span><br><span>@@ -0,0 +1,28 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PIC, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Remember the OS' IRQ routing choice. */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Arg0, PICM)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMI I/O Trap */</span><br><span style="color: hsl(120, 100%, 40%);">+Method(TRAP, 1, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Arg0, SMIF) /* SMI Function */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, TRP0) /* Generate trap */</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (SMIF) /* Return value of SMI handler */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/acpi/superio.asl b/src/mainboard/asus/p5qpl-am/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..2997587</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/acpi/superio.asl</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/* dummy */</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/acpi/x4x_pci_irqs.asl b/src/mainboard/asus/p5qpl-am/acpi/x4x_pci_irqs.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..5bec150</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/acpi/x4x_pci_irqs.asl</span><br><span>@@ -0,0 +1,66 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* This is board specific information: IRQ routing for x4x */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCI Interrupt Routing */</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PEG */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 0, 0, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Internal GFX */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 0, 0, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* High Definition Audio 0:1b.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001bffff, 0, 0, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIe Root Ports 0:1c.x */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001cffff, 0, 0, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001cffff, 1, 0, 0x11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001cffff, 2, 0, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001cffff, 3, 0, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB and EHCI 0:1d.x */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001dffff, 0, 0, 0x17 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001dffff, 1, 0, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001dffff, 2, 0, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001dffff, 3, 0, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PATA/SATA/SMBUS 0:1f.1-3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001fffff, 0, 0, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001fffff, 1, 0, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PEG */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Internal GFX */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* High Definition Audio 0:1b.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIe Root Ports 0:1c.x */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB and EHCI 0:1d.x */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PATA/SATA/SMBUS 0:1f.1-3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/acpi_tables.c b/src/mainboard/asus/p5qpl-am/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d80fb4c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/acpi_tables.c</span><br><span>@@ -0,0 +1,28 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "southbridge/intel/i82801gx/nvs.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ memset((void *)gnvs, 0, sizeof(*gnvs));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->pwrs = 1; /* Power state (AC = 1) */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->cmap = 0x01; /* Enable COM 1 port */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/board_info.txt b/src/mainboard/asus/p5qpl-am/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..cae9f22</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/board_info.txt</span><br><span>@@ -0,0 +1,7 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: desktop</span><br><span style="color: hsl(120, 100%, 40%);">+Board URL: https://www.asus.com/Motherboards/P5QPLAM/</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: DIP-8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: y</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2009</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/cmos.default b/src/mainboard/asus/p5qpl-am/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..1519fe1</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/cmos.default</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option=Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level=Spew</span><br><span style="color: hsl(120, 100%, 40%);">+power_on_after_fail=Disable</span><br><span style="color: hsl(120, 100%, 40%);">+nmi=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+gfx_uma_size=64M</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/cmos.layout b/src/mainboard/asus/p5qpl-am/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..57c30ae</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/cmos.layout</span><br><span>@@ -0,0 +1,105 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register A</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register B</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register C</span><br><span style="color: hsl(120, 100%, 40%);">+#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#100 1 r 0 uf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#101 1 r 0 af_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#102 1 r 0 pf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#103 1 r 0 irqf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register D</span><br><span style="color: hsl(120, 100%, 40%);">+#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Diagnostic Status Register</span><br><span style="color: hsl(120, 100%, 40%);">+#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 4 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+#390 5 r 0 unused?</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 6 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 7 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: cpu</span><br><span style="color: hsl(120, 100%, 40%);">+#424 1 e 2 hyper_threading</span><br><span style="color: hsl(120, 100%, 40%);">+#425 7 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+432 4 e 11 gfx_uma_size</span><br><span style="color: hsl(120, 100%, 40%);">+#435 549 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+1024 144 r 0 recv_enable_results</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+6 0 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+6 1 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+6 2 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+6 3 Error</span><br><span style="color: hsl(120, 100%, 40%);">+6 4 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+6 5 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+7 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+7 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+7 2 Keep</span><br><span style="color: hsl(120, 100%, 40%);">+11 6 64M</span><br><span style="color: hsl(120, 100%, 40%);">+11 7 128M</span><br><span style="color: hsl(120, 100%, 40%);">+11 8 256M</span><br><span style="color: hsl(120, 100%, 40%);">+11 9 96M</span><br><span style="color: hsl(120, 100%, 40%);">+11 10 160M</span><br><span style="color: hsl(120, 100%, 40%);">+11 11 224M</span><br><span style="color: hsl(120, 100%, 40%);">+11 12 352M</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 983 984</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/cstates.c b/src/mainboard/asus/p5qpl-am/cstates.c</span><br><span>new file mode 100644</span><br><span>index 0000000..128f655</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/cstates.c</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 secunet Security Networks AG</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpigen.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_cst_entries(acpi_cstate_t **entries)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..911e6fc</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/devicetree.cb</span><br><span>@@ -0,0 +1,139 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+# (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/x4x # Northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on # APIC cluster</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_LGA775</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_1067x # CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xACAC off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on # PCI domain</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1458 0x5000 inherit</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x2e30</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1.0 on end # PEG</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.0 on # Integrated graphics controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x2e32</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.0 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.1 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/i82801gx # Southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ide_enable_primary" = "0x1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_ports_implemented" = "0x3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_en" = "0x440"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on # Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x3662</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCIe 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on end # PCIe 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCIe 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCIe 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27c8</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 on # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27c9</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 on # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27ca</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 on # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27cb</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 on # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27cc</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # ISA bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27b8</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/winbond/w83627dhg</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 off end # Floppy</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 on # Parallel port</span><br><span style="color: hsl(120, 100%, 40%);">+ # global</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x28 = 0x70</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x2c = 0xd2</span><br><span style="color: hsl(120, 100%, 40%);">+ # parallel port</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x378</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 on # COM1</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 off end # COM2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # Keyboard & MOUSE</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x72 = 0x0C</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 off end # SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 off end # GPIO6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 off end # WDT0#, PLED</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.9 off end # GPIO2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.109 off end # GPIO3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.209 on # GPIO4</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf4 = 0x73</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.309 off end # GPIO5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a on # ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xe4 = 0x10 # Power dram during s3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.b on # HWM, front pannel LED</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x290</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.c off end # PECI, SST</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on # PATA/IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27df</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27c0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on # SMbus</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27da</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/ck505 # W83115RG-965</span><br><span style="color: hsl(120, 100%, 40%);">+ # set SATA to fixed 100Mhz refclk</span><br><span style="color: hsl(120, 100%, 40%);">+ register "mask" = "{ 0x02 }"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "regs" = "{ 0x02 }"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 69 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/dsdt.asl b/src/mainboard/asus/p5qpl-am/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e11eb39</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/dsdt.asl</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/i82801gx/i82801gx.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02, // DSDT revision: ACPI v2.0</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", // OEM id</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", // OEM table id</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20090419 // OEM revision</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // global NVS and variables</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/platform.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/x4x/acpi/x4x.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82801gx/acpi/ich7.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chipset specific sleep states */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/gpio.c b/src/mainboard/asus/p5qpl-am/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..97d553a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/gpio.c</span><br><span>@@ -0,0 +1,126 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/hda_verb.c b/src/mainboard/asus/p5qpl-am/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..1c0474b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/hda_verb.c</span><br><span>@@ -0,0 +1,72 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; either version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License, or (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* coreboot specific header */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Realtek ALC662 rev1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10ec0662, /* Vendor ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x18493662, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 10, /* Number of entries */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Widget Verb Table */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x18, 0x01a19830),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x19, 0x02a19940),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1b, 0x02214120),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* coreboot specific header */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Intel Eaglelake HDMI */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x80862803, /* Vendor ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x80860101, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000001, /* Number of entries */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Widget Verb Table */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(1, 0x03, 0x18560010),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* coreboot specific header */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Realtek ALC662 rev1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10ec0662, /* Vendor ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1565821e, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 10, /* Number of entries */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Widget Verb Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(2, 0x14, 0x01014410),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(2, 0x15, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(2, 0x16, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(2, 0x18, 0x01a19c30),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(2, 0x19, 0x02a19c40),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(2, 0x1a, 0x0181343f),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(2, 0x1c, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(2, 0x1e, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[0] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs);</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);</span><br><span>diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..4f8078e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qpl-am/romstage.c</span><br><span>@@ -0,0 +1,114 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/i82801gx/i82801gx.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/x4x/x4x.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/bist.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/nct6776/nct6776.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/winbond/w83627dhg/w83627dhg.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/winbond/common/winbond.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/common/nuvoton.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/stages.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/x4x/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pnp_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV PNP_DEV(0x2e, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mb_lpc_setup(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the value for GPIO base address register and enable GPIO. */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_pch_gpios(&mainboard_gpio_map);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set GPIOs on superio, enable UART */</span><br><span style="color: hsl(120, 100%, 40%);">+ winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IRQ routing */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(D31IR) = 0x0132;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(D29IR) = 0x0237;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable IOAPIC */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA8(OIC) = 0x03;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA8(OIC);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = RCBA32(GCS);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= (1 << 5);</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(GCS) = reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD</span><br><span style="color: hsl(120, 100%, 40%);">+ | FD_ACAUD | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(CG) = 0x00000001;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void ich7_enable_lpc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Decode range */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_romstage_entry(unsigned long bist)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // ch0 ch1</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 boot_path = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 s3_resume;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_init(get_initial_timestamp());</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_START_ROMSTAGE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set southbridge and Super I/O GPIOs. */</span><br><span style="color: hsl(120, 100%, 40%);">+ ich7_enable_lpc();</span><br><span style="color: hsl(120, 100%, 40%);">+ mb_lpc_setup();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ report_bist_failure(bist);</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_smbus();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ x4x_early_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ s3_resume = southbridge_detect_s3_resume();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s3_resume)</span><br><span style="color: hsl(120, 100%, 40%);">+ boot_path = BOOT_PATH_RESUME;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)</span><br><span style="color: hsl(120, 100%, 40%);">+ boot_path = BOOT_PATH_WARM_RESET;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Initializing memory\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_BEFORE_INITRAM);</span><br><span style="color: hsl(120, 100%, 40%);">+ sdram_initialize(boot_path, spd_addrmap);</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_AFTER_INITRAM);</span><br><span style="color: hsl(120, 100%, 40%);">+ quick_ram_check();</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Memory initialized\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ x4x_late_init(s3_resume);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "x4x late init complete\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25659">change 25659</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I160f9201e812f44ef9842caef851750fb7690c9e </div>
<div style="display:none"> Gerrit-Change-Number: 25659 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: AndiR <andir@memeware.net> </div>