<p>Evan Green has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25639">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Revert "arch/arm64/armv8/mmu: Add support for 48bit VA"<br><br>This reverts commit 57afc5e0f2309ba9f7fbd171642f04c6da9d9976.<br><br>Change-Id: I7c3a04d7d55b10736ed68ba96f892e2aaa1e3e2d<br>---<br>M payloads/libpayload/arch/arm64/mmu.c<br>M payloads/libpayload/include/arm64/arch/mmu.h<br>M src/arch/arm64/armv8/mmu.c<br>M src/arch/arm64/include/armv8/arch/mmu.h<br>4 files changed, 37 insertions(+), 37 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/25639/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c</span><br><span>index c860ee0..d84f969 100644</span><br><span>--- a/payloads/libpayload/arch/arm64/mmu.c</span><br><span>+++ b/payloads/libpayload/arch/arm64/mmu.c</span><br><span>@@ -172,7 +172,6 @@</span><br><span> uint64_t size,</span><br><span> uint64_t tag)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uint64_t l0_index = (base_addr & L0_ADDR_MASK) >> L0_ADDR_SHIFT;</span><br><span> uint64_t l1_index = (base_addr & L1_ADDR_MASK) >> L1_ADDR_SHIFT;</span><br><span> uint64_t l2_index = (base_addr & L2_ADDR_MASK) >> L2_ADDR_SHIFT;</span><br><span> uint64_t l3_index = (base_addr & L3_ADDR_MASK) >> L3_ADDR_SHIFT;</span><br><span>@@ -180,12 +179,12 @@</span><br><span> uint64_t desc;</span><br><span> uint64_t attr = get_block_attr(tag);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* L0 entry stores a table descriptor (doesn't support blocks) */</span><br><span style="color: hsl(0, 100%, 40%);">- table = get_next_level_table(&table[l0_index], L1_XLAT_SIZE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* L1 table lookup */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((size >= L1_XLAT_SIZE) &&</span><br><span style="color: hsl(0, 100%, 40%);">- IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* L1 table lookup</span><br><span style="color: hsl(120, 100%, 40%);">+ * If VA has bits more than L2 can resolve, lookup starts at L1</span><br><span style="color: hsl(120, 100%, 40%);">+ * Assumption: we don't need L0 table in coreboot */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (BITS_PER_VA > L1_ADDR_SHIFT) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((size >= L1_XLAT_SIZE) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) {</span><br><span> /* If block address is aligned and size is greater than</span><br><span> * or equal to size addressed by each L1 entry, we can</span><br><span> * directly store a block desc */</span><br><span>@@ -193,12 +192,13 @@</span><br><span> table[l1_index] = desc;</span><br><span> /* L2 lookup is not required */</span><br><span> return L1_XLAT_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* L1 entry stores a table descriptor */</span><br><span style="color: hsl(0, 100%, 40%);">- table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* L2 table lookup */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* L2 table lookup</span><br><span style="color: hsl(120, 100%, 40%);">+ * If lookup was performed at L1, L2 table addr is obtained from L1 desc</span><br><span style="color: hsl(120, 100%, 40%);">+ * else, lookup starts at ttbr address */</span><br><span> if ((size >= L2_XLAT_SIZE) &&</span><br><span> IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) {</span><br><span> /* If block address is aligned and size is greater than</span><br><span>@@ -226,7 +226,6 @@</span><br><span> {</span><br><span> assert(!(addr & GRANULE_SIZE_MASK) &&</span><br><span> !(size & GRANULE_SIZE_MASK) &&</span><br><span style="color: hsl(0, 100%, 40%);">- (addr + size < (1UL << BITS_PER_VA)) &&</span><br><span> size >= GRANULE_SIZE);</span><br><span> }</span><br><span> </span><br><span>@@ -345,7 +344,7 @@</span><br><span> </span><br><span> /* Initialize TCR flags */</span><br><span> raw_write_tcr_current(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC |</span><br><span style="color: hsl(0, 100%, 40%);">- TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_256TB |</span><br><span style="color: hsl(120, 100%, 40%);">+ TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_64GB |</span><br><span> TCR_TBI_USED);</span><br><span> </span><br><span> /* Initialize TTBR */</span><br><span>diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h</span><br><span>index 3cea696..2f87d09 100644</span><br><span>--- a/payloads/libpayload/include/arm64/arch/mmu.h</span><br><span>+++ b/payloads/libpayload/include/arm64/arch/mmu.h</span><br><span>@@ -83,7 +83,7 @@</span><br><span> /* XLAT Table Init Attributes */</span><br><span> </span><br><span> #define VA_START 0x0</span><br><span style="color: hsl(0, 100%, 40%);">-#define BITS_PER_VA 48</span><br><span style="color: hsl(120, 100%, 40%);">+#define BITS_PER_VA 33</span><br><span> #define MIN_64_BIT_ADDR (1UL << 32)</span><br><span> /* Granule size of 4KB is being used */</span><br><span> #define GRANULE_SIZE_SHIFT 12</span><br><span>@@ -92,12 +92,14 @@</span><br><span> #define GRANULE_SIZE_MASK ((1 << GRANULE_SIZE_SHIFT) - 1)</span><br><span> </span><br><span> #define BITS_RESOLVED_PER_LVL (GRANULE_SIZE_SHIFT - 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define L0_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 3)</span><br><span> #define L1_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 2)</span><br><span> #define L2_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 1)</span><br><span> #define L3_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 0)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define L0_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L0_ADDR_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#if BITS_PER_VA > L1_ADDR_SHIFT + BITS_RESOLVED_PER_LVL</span><br><span style="color: hsl(120, 100%, 40%);">+ #error "BITS_PER_VA too large (we don't have L0 table support)"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define L1_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT)</span><br><span> #define L2_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT)</span><br><span> #define L3_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT)</span><br><span>@@ -107,7 +109,6 @@</span><br><span> #define L3_XLAT_SIZE (1UL << L3_ADDR_SHIFT)</span><br><span> #define L2_XLAT_SIZE (1UL << L2_ADDR_SHIFT)</span><br><span> #define L1_XLAT_SIZE (1UL << L1_ADDR_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define L0_XLAT_SIZE (1UL << L0_ADDR_SHIFT)</span><br><span> </span><br><span> /* Block indices required for MAIR */</span><br><span> #define BLOCK_INDEX_MEM_DEV_NGNRNE 0</span><br><span>diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c</span><br><span>index a24e7c6..55bd703 100644</span><br><span>--- a/src/arch/arm64/armv8/mmu.c</span><br><span>+++ b/src/arch/arm64/armv8/mmu.c</span><br><span>@@ -141,7 +141,6 @@</span><br><span> uint64_t size,</span><br><span> uint64_t tag)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uint64_t l0_index = (base_addr & L0_ADDR_MASK) >> L0_ADDR_SHIFT;</span><br><span> uint64_t l1_index = (base_addr & L1_ADDR_MASK) >> L1_ADDR_SHIFT;</span><br><span> uint64_t l2_index = (base_addr & L2_ADDR_MASK) >> L2_ADDR_SHIFT;</span><br><span> uint64_t l3_index = (base_addr & L3_ADDR_MASK) >> L3_ADDR_SHIFT;</span><br><span>@@ -149,12 +148,12 @@</span><br><span> uint64_t desc;</span><br><span> uint64_t attr = get_block_attr(tag);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* L0 entry stores a table descriptor (doesn't support blocks) */</span><br><span style="color: hsl(0, 100%, 40%);">- table = get_next_level_table(&table[l0_index], L1_XLAT_SIZE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* L1 table lookup */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((size >= L1_XLAT_SIZE) &&</span><br><span style="color: hsl(0, 100%, 40%);">- IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* L1 table lookup</span><br><span style="color: hsl(120, 100%, 40%);">+ * If VA has bits more than L2 can resolve, lookup starts at L1</span><br><span style="color: hsl(120, 100%, 40%);">+ * Assumption: we don't need L0 table in coreboot */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (BITS_PER_VA > L1_ADDR_SHIFT) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((size >= L1_XLAT_SIZE) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) {</span><br><span> /* If block address is aligned and size is greater than</span><br><span> * or equal to size addressed by each L1 entry, we can</span><br><span> * directly store a block desc */</span><br><span>@@ -162,12 +161,13 @@</span><br><span> table[l1_index] = desc;</span><br><span> /* L2 lookup is not required */</span><br><span> return L1_XLAT_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* L1 entry stores a table descriptor */</span><br><span style="color: hsl(0, 100%, 40%);">- table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* L2 table lookup */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* L2 table lookup</span><br><span style="color: hsl(120, 100%, 40%);">+ * If lookup was performed at L1, L2 table addr is obtained from L1 desc</span><br><span style="color: hsl(120, 100%, 40%);">+ * else, lookup starts at ttbr address */</span><br><span> if ((size >= L2_XLAT_SIZE) &&</span><br><span> IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) {</span><br><span> /* If block address is aligned and size is greater than</span><br><span>@@ -195,7 +195,6 @@</span><br><span> {</span><br><span> assert(!(addr & GRANULE_SIZE_MASK) &&</span><br><span> !(size & GRANULE_SIZE_MASK) &&</span><br><span style="color: hsl(0, 100%, 40%);">- (addr + size < (1UL << BITS_PER_VA)) &&</span><br><span> size >= GRANULE_SIZE);</span><br><span> }</span><br><span> </span><br><span>@@ -203,7 +202,7 @@</span><br><span> * Desc : Returns the page table entry governing a specific address. */</span><br><span> static uint64_t get_pte(void *addr)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- int shift = L0_ADDR_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ int shift = BITS_PER_VA > L1_ADDR_SHIFT ? L1_ADDR_SHIFT : L2_ADDR_SHIFT;</span><br><span> uint64_t *pte = (uint64_t *)_ttb;</span><br><span> </span><br><span> while (1) {</span><br><span>@@ -258,8 +257,8 @@</span><br><span> for (; _ettb - (u8 *)table > 0; table += GRANULE_SIZE/sizeof(*table))</span><br><span> table[0] = UNUSED_DESC;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Initialize the root table (L0) to be completely unmapped. */</span><br><span style="color: hsl(0, 100%, 40%);">- uint64_t *root = setup_new_table(INVALID_DESC, L0_XLAT_SIZE);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the root table (L1) to be completely unmapped. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t *root = setup_new_table(INVALID_DESC, L1_XLAT_SIZE);</span><br><span> assert((u8 *)root == _ttb);</span><br><span> </span><br><span> /* Initialize TTBR */</span><br><span>@@ -270,7 +269,7 @@</span><br><span> </span><br><span> /* Initialize TCR flags */</span><br><span> raw_write_tcr_el3(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC |</span><br><span style="color: hsl(0, 100%, 40%);">- TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_256TB |</span><br><span style="color: hsl(120, 100%, 40%);">+ TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_64GB |</span><br><span> TCR_TBI_USED);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h</span><br><span>index f0e551e..a812073 100644</span><br><span>--- a/src/arch/arm64/include/armv8/arch/mmu.h</span><br><span>+++ b/src/arch/arm64/include/armv8/arch/mmu.h</span><br><span>@@ -69,7 +69,7 @@</span><br><span> /* XLAT Table Init Attributes */</span><br><span> </span><br><span> #define VA_START 0x0</span><br><span style="color: hsl(0, 100%, 40%);">-#define BITS_PER_VA 48</span><br><span style="color: hsl(120, 100%, 40%);">+#define BITS_PER_VA 33</span><br><span> /* Granule size of 4KB is being used */</span><br><span> #define GRANULE_SIZE_SHIFT 12</span><br><span> #define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT)</span><br><span>@@ -77,12 +77,14 @@</span><br><span> #define GRANULE_SIZE_MASK ((1 << GRANULE_SIZE_SHIFT) - 1)</span><br><span> </span><br><span> #define BITS_RESOLVED_PER_LVL (GRANULE_SIZE_SHIFT - 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define L0_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 3)</span><br><span> #define L1_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 2)</span><br><span> #define L2_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 1)</span><br><span> #define L3_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 0)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define L0_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L0_ADDR_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#if BITS_PER_VA > L1_ADDR_SHIFT + BITS_RESOLVED_PER_LVL</span><br><span style="color: hsl(120, 100%, 40%);">+ #error "BITS_PER_VA too large (we don't have L0 table support)"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define L1_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT)</span><br><span> #define L2_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT)</span><br><span> #define L3_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT)</span><br><span>@@ -92,7 +94,6 @@</span><br><span> #define L3_XLAT_SIZE (1UL << L3_ADDR_SHIFT)</span><br><span> #define L2_XLAT_SIZE (1UL << L2_ADDR_SHIFT)</span><br><span> #define L1_XLAT_SIZE (1UL << L1_ADDR_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define L0_XLAT_SIZE (1UL << L0_ADDR_SHIFT)</span><br><span> </span><br><span> /* Block indices required for MAIR */</span><br><span> #define BLOCK_INDEX_MEM_DEV_NGNRNE 0</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25639">change 25639</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7c3a04d7d55b10736ed68ba96f892e2aaa1e3e2d </div>
<div style="display:none"> Gerrit-Change-Number: 25639 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Evan Green <evgreen@chromium.org> </div>