<p>Venkateswarlu V Vinjamuri has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25638">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Configure PCIe root port #3 for GLK WiFi<br><br>GLK Octopus uses PCIe root port #3 (PCIe ID 13.0) for discrete PCIe<br>wifi card.<br><br>BUG=None<br>BRANCH=None<br>TEST=Use Stone Peak discrete wifi card and test s0ix.<br><br>Change-Id: I8a064c5d97e4765bd97ec560c89b207b574b1fa1<br>Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com><br>---<br>M src/soc/intel/apollolake/acpi/pcie.asl<br>M src/soc/intel/apollolake/chip.c<br>2 files changed, 11 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/25638/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl</span><br><span>index da99591..539ae9b 100644</span><br><span>--- a/src/soc/intel/apollolake/acpi/pcie.asl</span><br><span>+++ b/src/soc/intel/apollolake/acpi/pcie.asl</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span>  * This file is part of the coreboot project.</span><br><span>  *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2016 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Intel Corporation</span><br><span>  *</span><br><span>  * This program is free software; you can redistribute it and/or modify</span><br><span>  * it under the terms of the GNU General Public License as published by</span><br><span>@@ -22,3 +22,11 @@</span><br><span> </span><br><span>        #include "pcie_port.asl"</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP03)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+   Name (_ADR, 0x00130000)</span><br><span style="color: hsl(120, 100%, 40%);">+       Name (_DDN, "PCIe-A 0")</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   #include "pcie_port.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c</span><br><span>index 324fb9f..2c90b48 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.c</span><br><span>+++ b/src/soc/intel/apollolake/chip.c</span><br><span>@@ -111,6 +111,8 @@</span><br><span>         case PCH_DEVFN_SDIO:</span><br><span>                 return "SDIO";</span><br><span>     /* PCIe */</span><br><span style="color: hsl(120, 100%, 40%);">+    case PCH_DEVFN_PCIE1:</span><br><span style="color: hsl(120, 100%, 40%);">+         return "RP03";</span><br><span>     case PCH_DEVFN_PCIE5:</span><br><span>                return "RP01";</span><br><span>     }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25638">change 25638</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25638"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8a064c5d97e4765bd97ec560c89b207b574b1fa1 </div>
<div style="display:none"> Gerrit-Change-Number: 25638 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> </div>