<p>Shelley Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25646">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy/variants/nami: Update GPIOs<br><br>Updating some GPIOs based on changes in the latest schematics<br><br>BUG=b:73749640<br>BRANCH=None<br>TEST=./util/abuild/abuild -p none -t google/poppy -x -a<br><br>Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d<br>Signed-off-by: Shelley Chen <shchen@google.com><br>---<br>M src/mainboard/google/poppy/variants/nami/gpio.c<br>1 file changed, 61 insertions(+), 59 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/25646/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c</span><br><span>index 37a9420..229c4ee 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nami/gpio.c</span><br><span>+++ b/src/mainboard/google/poppy/variants/nami/gpio.c</span><br><span>@@ -50,8 +50,8 @@</span><br><span> PAD_CFG_NC(GPP_A16),</span><br><span> /* A17 : SD_PWR_EN# ==> NC */</span><br><span> PAD_CFG_NC(GPP_A17),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A18 : ISH_GP0 ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_A18),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A18 : ISH_GP0 ==> EMMC_RST#L_R_SOC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_A18, 1, DEEP),</span><br><span> /* A19 : ISH_GP1 ==> NC */</span><br><span> PAD_CFG_NC(GPP_A19),</span><br><span> /* A20 : ISH_GP2 ==> NC */</span><br><span>@@ -91,8 +91,8 @@</span><br><span> PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span> /* B13 : PLTRST# ==> PLT_RST#_PCH */</span><br><span> PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* B14 : SPKR ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_B14),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B14 : SPKR ==> EC_GPP_B14 / PP3300_S */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP),</span><br><span> /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */</span><br><span> PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),</span><br><span> /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */</span><br><span>@@ -109,21 +109,21 @@</span><br><span> PAD_CFG_NC(GPP_B21),</span><br><span> /* B22 : GSPI1_MOSI ==> NC(TP30) */</span><br><span> PAD_CFG_NC(GPP_B22),</span><br><span style="color: hsl(0, 100%, 40%);">- /* B23 : SM1ALERT# ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_B23),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B23 : SM1ALERT# ==> SOC_SML1ALERT# */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* C0 : SMBCLK ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_C0),</span><br><span style="color: hsl(0, 100%, 40%);">- /* C1 : SMBDATA ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_C1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C0 : SMBCLK ==> SOC_SMBCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C1 : SMBDATA ==> SOC_SMBDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),</span><br><span> /* C2 : SMBALERT# ==> NC(TP917) */</span><br><span> PAD_CFG_NC(GPP_C2),</span><br><span> /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */</span><br><span> PAD_CFG_GPO(GPP_C3, 0, DEEP),</span><br><span> /* C4 : SML0DATA ==> NC */</span><br><span> PAD_CFG_NC(GPP_C4),</span><br><span style="color: hsl(0, 100%, 40%);">- /* C5 : SML0ALERT# ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_C5),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C5 : SML0ALERT# ==> SOC_SML0ALERT# */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),</span><br><span> /* C6 : SM1CLK ==> EC_IN_RW_OD */</span><br><span> PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),</span><br><span> /* C7 : SM1DATA ==> TRACKPAD_DISABLE# */</span><br><span>@@ -156,13 +156,13 @@</span><br><span> PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),</span><br><span> /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */</span><br><span> PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* C22 : UART2_RTS# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C22 : UART2_RTS# ==> NC(TP926) */</span><br><span> PAD_CFG_NC(GPP_C22),</span><br><span> /* C23 : UART2_CTS# ==> PCH_WP */</span><br><span> PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* D0 : SPI1_CS# ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_D0),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D0 : SPI1_CS# ==> DDR_CHB_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D0, NONE, DEEP),</span><br><span> /* D1 : SPI1_CLK ==> PEN_IRQ# */</span><br><span> PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST),</span><br><span> /* D2 : SPI1_MISO ==> PEN_PDCT# */</span><br><span>@@ -181,45 +181,47 @@</span><br><span> PAD_CFG_NC(GPP_D8),</span><br><span> /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */</span><br><span> PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D10 : ISH_SPI_CLK ==> NC(TP29) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_D10),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D11 : ISH_SPI_MISO ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_D11),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D12 : ISH_SPI_MOSI ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_D12),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D13 : ISH_UART0_RXD ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_D13),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D14 : ISH_UART0_TXD ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_D14),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D11 : ISH_SPI_MISO ==> DCI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D12 : ISH_SPI_MOSI ==> DCI_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D13 : ISH_UART0_RXD ==> H1_BOOT_UART_RX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D14 : ISH_UART0_TXD ==> H1_BOOT_UART_TX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),</span><br><span> /* D15 : ISH_UART0_RTS# ==> NC */</span><br><span> PAD_CFG_NC(GPP_D15),</span><br><span> /* D16 : ISH_UART0_CTS# ==> NC */</span><br><span> PAD_CFG_NC(GPP_D16),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D18 : DMIC_DATA1 ==> SOC_DMIC_DATA1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D17 : DMIC_DATA1 ==> SOC_DMIC_CLK1_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D18 : DMIC_DATA1 ==> SOC_DMIC_DATA1_R */</span><br><span> PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D19 : DMIC_CLK0 ==> SOC_DMIC_CLK0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D19 : DMIC_CLK0 ==> SOC_DMIC_CLK0_R */</span><br><span> PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D20 : DMIC_DATA0 ==> SOC_DMIC_DATA0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D20 : DMIC_DATA0 ==> SOC_DMIC_DATA0_R */</span><br><span> PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D21 : SPI1_IO2 ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_D21),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D21 : SPI1_IO2 ==> DDR_CHA_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D21, NONE, DEEP),</span><br><span> /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */</span><br><span> PAD_CFG_GPO(GPP_D22, 1, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D23 : I2S_MCLK ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D23 : I2S_MCLK ==> I2S_1_MCLK */</span><br><span> PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),</span><br><span> </span><br><span> /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */</span><br><span> PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),</span><br><span> /* E1 : SATAXPCIE1 ==> PEN_EJECT_ODL - for wake event */</span><br><span> PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E2 : SATAXPCIE2 ==> NC(TP916) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_E2),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E2 : SATAXPCIE2 ==> WLAN_OFF# */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_E2, 0, DEEP),</span><br><span> /* E3 : CPU_GP0 ==> TRACKPAD_INT# */</span><br><span> PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST),</span><br><span> /* E4 : SATA_DEVSLP0 ==> NC(TP914) */</span><br><span> PAD_CFG_NC(GPP_E4),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E5 : SATA_DEVSLP1 ==> DEVSLP1 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E5 : SATA_DEVSLP1 ==> NC(TP928) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E5),</span><br><span> /* E6 : SATA_DEVSLP2 ==> NC(TP915) */</span><br><span> PAD_CFG_NC(GPP_E6),</span><br><span> /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT# */</span><br><span>@@ -238,10 +240,10 @@</span><br><span> PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),</span><br><span> /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */</span><br><span> PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E15 : DDPD_HPD2 ==> PCH_MEM_CONFIG4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E15 : DDPD_HPD2 ==> DDR_SEL */</span><br><span> PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E16 : DDPE_HPD3 ==> PCH_GPP_E16 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, INVERT),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E16 : DDPE_HPD3 ==> TRACKPAD_INT# */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, INVERT),</span><br><span> /* E17 : EDP_HPD ==> EDP_HPD */</span><br><span> PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span> /* E18 : DDPB_CTRLCLK ==> SOC_DP1_CTRL_CLK */</span><br><span>@@ -254,15 +256,15 @@</span><br><span> PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),</span><br><span> /* E22 : DDPD_CTRLCLK ==> WLAN_PCIE_WAKE# */</span><br><span> PAD_CFG_GPI_ACPI_SCI(GPP_E22, NONE, DEEP, INVERT),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E23 : DDPD_CTRLDATA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E23 : DDPD_CTRLDATA ==> NC(TP17)*/</span><br><span> PAD_CFG_NC(GPP_E23),</span><br><span> </span><br><span> /* The next 4 pads are for bit banging the amplifiers, default to I2S */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F0 : I2S2_SCLK ==> I2S2_2_BCLK_R */</span><br><span> PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F1 : I2S2_SFRM ==> I2S2_2_FS_LRC */</span><br><span> PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F2 : I2S2_TXD ==> I2S2_2_TX_DAC */</span><br><span> PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),</span><br><span> /* F3 : I2S2_RXD ==> NC */</span><br><span> PAD_CFG_NC(GPP_F3),</span><br><span>@@ -274,35 +276,35 @@</span><br><span> PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),</span><br><span> /* F7 : I2C3_SCL ==> I2C_3_SCL */</span><br><span> PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F8 : I2C4_SDA ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_F8),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F9 : I2C4_SCL ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_F9),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F8 : I2C4_SDA ==> I2C_4_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F9 : I2C4_SCL ==> I2C_4_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),</span><br><span> /* F10 : I2C5_SDA ==> NC */</span><br><span> PAD_CFG_NC(GPP_F10),</span><br><span> /* F11 : I2C5_SCL ==> NC */</span><br><span> PAD_CFG_NC(GPP_F11),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F12 : EMMC_CMD ==> EMMC_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F12 : EMMC_CMD ==> EMMC_1_CMD */</span><br><span> PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F13 : EMMC_DATA0 ==> EMMC_DATA0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F13 : EMMC_DATA0 ==> EMMC_1_D0 */</span><br><span> PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F14 : EMMC_DATA1 ==> EMMC_DATA1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F14 : EMMC_DATA1 ==> EMMC_1_D1 */</span><br><span> PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F15 : EMMC_DATA2 ==> EMMC_DATA2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F15 : EMMC_DATA2 ==> EMMC_1_D2 */</span><br><span> PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F16 : EMMC_DATA3 ==> EMMC_DATA3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F16 : EMMC_DATA3 ==> EMMC_1_D3 */</span><br><span> PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F17 : EMMC_DATA4 ==> EMMC_DATA4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F17 : EMMC_DATA4 ==> EMMC_1_D4 */</span><br><span> PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F18 : EMMC_DATA5 ==> EMMC_DATA5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F18 : EMMC_DATA5 ==> EMMC_1_D5 */</span><br><span> PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F19 : EMMC_DATA6 ==> EMMC_DATA6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F19 : EMMC_DATA6 ==> EMMC_1_D6 */</span><br><span> PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F20 : EMMC_DATA7 ==> EMMC_DATA7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F20 : EMMC_DATA7 ==> EMMC_1_D7 */</span><br><span> PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F21 : EMMC_RCLK ==> EMMC_RCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F21 : EMMC_RCLK ==> EMMC_1_RCLK */</span><br><span> PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F22 : EMMC_CLK ==> EMMC_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F22 : EMMC_CLK ==> EMMC_1_CLK */</span><br><span> PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),</span><br><span> /* F23 : RSVD ==> NC */</span><br><span> PAD_CFG_NC(GPP_F23),</span><br><span>@@ -321,8 +323,8 @@</span><br><span> PAD_CFG_NC(GPP_G5),</span><br><span> /* G6 : SD_CLK ==> NC */</span><br><span> PAD_CFG_NC(GPP_G6),</span><br><span style="color: hsl(0, 100%, 40%);">- /* G7 : SD_WP ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_G7),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G7 : SD_WP ==> SD_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_G7, NONE, DEEP),</span><br><span> </span><br><span> /* GPD0: BATLOW# ==> PCH_BATLOW# */</span><br><span> PAD_CFG_NF(GPD0, NONE, DEEP, NF1),</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25646">change 25646</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d </div>
<div style="display:none"> Gerrit-Change-Number: 25646 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Shelley Chen <shchen@google.com> </div>