<p>Arthur Heymans <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/25616">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Revert "model_206ax: Use parallel MP init"<br><br>This reverts commit 5fbe788bae15f0d24d56011e8eb8b48c107b7b05.<br>This commit was submitted without its parent being submitted,<br>resulting in coreboot not building.<br><br>Change-Id: I87497093ccf6909b88e3a40d5f472afeb7f2c552<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>Reviewed-on: https://review.coreboot.org/25616<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/cpu/intel/fsp_model_206ax/model_206ax.h<br>M src/cpu/intel/model_2065x/model_2065x.h<br>M src/cpu/intel/model_206ax/Kconfig<br>M src/cpu/intel/model_206ax/model_206ax.h<br>M src/cpu/intel/model_206ax/model_206ax_init.c<br>M src/cpu/intel/smm/gen1/smi.h<br>M src/cpu/intel/smm/gen1/smmrelocate.c<br>M src/northbridge/intel/sandybridge/northbridge.c<br>M src/southbridge/intel/bd82x6x/elog.c<br>M src/southbridge/intel/bd82x6x/pch.h<br>M src/southbridge/intel/common/pmutil.h<br>M src/southbridge/intel/common/smi.c<br>12 files changed, 93 insertions(+), 194 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>index 3d6166d..e65b370 100644</span><br><span>--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>@@ -102,6 +102,7 @@</span><br><span> /* Configure power limits for turbo mode */</span><br><span> void set_power_limits(u8 power_limit_1_time);</span><br><span> int cpu_config_tdp_levels(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_relocate(void);</span><br><span> #endif</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>index 861414d..8bb3b87 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>@@ -91,6 +91,7 @@</span><br><span> /* Configure power limits for turbo mode */</span><br><span> void set_power_limits(u8 power_limit_1_time);</span><br><span> int cpu_config_tdp_levels(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_relocate(void);</span><br><span> #endif</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig</span><br><span>index cb09d23..b30cfa1 100644</span><br><span>--- a/src/cpu/intel/model_206ax/Kconfig</span><br><span>+++ b/src/cpu/intel/model_206ax/Kconfig</span><br><span>@@ -23,7 +23,6 @@</span><br><span> select TSC_SYNC_MFENCE</span><br><span> select CPU_INTEL_COMMON</span><br><span> select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</span><br><span style="color: hsl(0, 100%, 40%);">- select PARALLEL_MP</span><br><span> </span><br><span> config BOOTBLOCK_CPU_INIT</span><br><span> string</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>index e5bc39e..962b830 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>@@ -121,6 +121,7 @@</span><br><span> /* Configure power limits for turbo mode */</span><br><span> void set_power_limits(u8 power_limit_1_time);</span><br><span> int cpu_config_tdp_levels(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_relocate(void);</span><br><span> #endif</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c</span><br><span>index 2b8e55b..5c60ed7 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax_init.c</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax_init.c</span><br><span>@@ -15,7 +15,6 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <assert.h></span><br><span> #include <console/console.h></span><br><span> #include <device/device.h></span><br><span> #include <string.h></span><br><span>@@ -24,7 +23,6 @@</span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/mp.h></span><br><span> #include <cpu/intel/microcode.h></span><br><span> #include <cpu/intel/speedstep.h></span><br><span> #include <cpu/intel/turbo.h></span><br><span>@@ -423,6 +421,83 @@</span><br><span> wrmsr(IA32_MC0_STATUS + (i * 4), msr);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+int cpu_get_apic_id_map(int *apic_id_map)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cpuid_result result;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int threads_per_package, threads_per_core, i, shift = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Logical processors (threads) per core */</span><br><span style="color: hsl(120, 100%, 40%);">+ result = cpuid_ext(0xb, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ threads_per_core = result.ebx & 0xffff;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Logical processors (threads) per package */</span><br><span style="color: hsl(120, 100%, 40%);">+ result = cpuid_ext(0xb, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ threads_per_package = result.ebx & 0xffff;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (threads_per_core == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ shift++;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < threads_per_package && i < CONFIG_MAX_CPUS; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ apic_id_map[i] = i << shift;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return threads_per_package;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Initialize any extra cores/threads in this package.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_cores_init(struct device *cpu)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cpuid_result result;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int threads_per_package, threads_per_core, i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Logical processors (threads) per core */</span><br><span style="color: hsl(120, 100%, 40%);">+ result = cpuid_ext(0xb, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ threads_per_core = result.ebx & 0xffff;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Logical processors (threads) per package */</span><br><span style="color: hsl(120, 100%, 40%);">+ result = cpuid_ext(0xb, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ threads_per_package = result.ebx & 0xffff;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Only initialize extra cores from BSP */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cpu->path.apic.apic_id)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu->path.apic.apic_id, threads_per_package/threads_per_core,</span><br><span style="color: hsl(120, 100%, 40%);">+ threads_per_core);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 1; i < threads_per_package; ++i) {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device_path cpu_path;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *new;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Build the CPU device path */</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_path.type = DEVICE_PATH_APIC;</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_path.apic.apic_id =</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu->path.apic.apic_id + i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Update APIC ID if no hyperthreading */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (threads_per_core == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_path.apic.apic_id <<= 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Allocate the new CPU device structure */</span><br><span style="color: hsl(120, 100%, 40%);">+ new = alloc_dev(cpu->bus, &cpu_path);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!new)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "CPU: %u has core %u\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu->path.apic.apic_id,</span><br><span style="color: hsl(120, 100%, 40%);">+ new->path.apic.apic_id);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Start the new CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (is_smp_boot() && !start_cpu(new)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Record the error in cpu? */</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "CPU %u would not start!\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ new->path.apic.apic_id);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void model_206ax_init(struct device *cpu)</span><br><span> {</span><br><span> char processor_name[49];</span><br><span>@@ -430,6 +505,8 @@</span><br><span> /* Turn on caching if we haven't already */</span><br><span> x86_enable_cache();</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ intel_update_microcode_from_cbfs();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Clear out pending MCEs */</span><br><span> configure_mca();</span><br><span> </span><br><span>@@ -437,6 +514,10 @@</span><br><span> fill_processor_name(processor_name);</span><br><span> printk(BIOS_INFO, "CPU: %s.\n", processor_name);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setup MTRRs based on physical address size */</span><br><span style="color: hsl(120, 100%, 40%);">+ x86_setup_mtrrs_with_detect();</span><br><span style="color: hsl(120, 100%, 40%);">+ x86_mtrr_check();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Setup Page Attribute Tables (PAT) */</span><br><span> // TODO set up PAT</span><br><span> </span><br><span>@@ -467,81 +548,9 @@</span><br><span> </span><br><span> /* Enable Turbo */</span><br><span> enable_turbo();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* MP initialization support. */</span><br><span style="color: hsl(0, 100%, 40%);">-static const void *microcode_patch;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void pre_mp_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup MTRRs based on physical address size. */</span><br><span style="color: hsl(0, 100%, 40%);">- x86_setup_mtrrs_with_detect();</span><br><span style="color: hsl(0, 100%, 40%);">- x86_mtrr_check();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int get_cpu_count(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct cpuid_result result;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int threads_per_package, threads_per_core;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Logical processors (threads) per core */</span><br><span style="color: hsl(0, 100%, 40%);">- result = cpuid_ext(0xb, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- threads_per_core = result.ebx & 0xffff;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- ASSERT(threads_per_core != 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Logical processors (threads) per package */</span><br><span style="color: hsl(0, 100%, 40%);">- result = cpuid_ext(0xb, 1);</span><br><span style="color: hsl(0, 100%, 40%);">- threads_per_package = result.ebx & 0xffff;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",</span><br><span style="color: hsl(0, 100%, 40%);">- threads_per_package / threads_per_core, threads_per_package);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return threads_per_package;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void get_microcode_info(const void **microcode, int *parallel)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- microcode_patch = intel_microcode_find();</span><br><span style="color: hsl(0, 100%, 40%);">- *microcode = microcode_patch;</span><br><span style="color: hsl(0, 100%, 40%);">- *parallel = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void per_cpu_smm_trigger(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Relocate the SMM handler. */</span><br><span style="color: hsl(0, 100%, 40%);">- smm_relocate();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* After SMM relocation a 2nd microcode load is required. */</span><br><span style="color: hsl(0, 100%, 40%);">- intel_microcode_load_unlocked(microcode_patch);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void post_mp_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Now that all APs have been relocated as well as the BSP let SMIs</span><br><span style="color: hsl(0, 100%, 40%);">- * start flowing. */</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smm_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Lock down the SMRAM space. */</span><br><span style="color: hsl(0, 100%, 40%);">- smm_lock();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct mp_ops mp_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- .pre_mp_init = pre_mp_init,</span><br><span style="color: hsl(0, 100%, 40%);">- .get_cpu_count = get_cpu_count,</span><br><span style="color: hsl(0, 100%, 40%);">- .get_smm_info = smm_info,</span><br><span style="color: hsl(0, 100%, 40%);">- .get_microcode_info = get_microcode_info,</span><br><span style="color: hsl(0, 100%, 40%);">- .pre_mp_smm_init = smm_initialize,</span><br><span style="color: hsl(0, 100%, 40%);">- .per_cpu_smm_trigger = per_cpu_smm_trigger,</span><br><span style="color: hsl(0, 100%, 40%);">- .relocation_handler = smm_relocation_handler,</span><br><span style="color: hsl(0, 100%, 40%);">- .post_mp_init = post_mp_init,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void bsp_init_and_start_aps(struct bus *cpu_bus)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- if (mp_init_with_smm(cpu_bus, &mp_ops))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "MP initialization failure.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Start up extra cores */</span><br><span style="color: hsl(120, 100%, 40%);">+ intel_cores_init(cpu);</span><br><span> }</span><br><span> </span><br><span> static struct device_operations cpu_dev_ops = {</span><br><span>diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h</span><br><span>index a63e731..c328eae 100644</span><br><span>--- a/src/cpu/intel/smm/gen1/smi.h</span><br><span>+++ b/src/cpu/intel/smm/gen1/smi.h</span><br><span>@@ -11,10 +11,6 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void bsp_init_and_start_aps(struct bus *cpu_bus);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* These helpers are for performing SMM relocation. */</span><br><span> void southbridge_smm_init(void);</span><br><span> void southbridge_trigger_smi(void);</span><br><span>@@ -22,10 +18,3 @@</span><br><span> u32 northbridge_get_tseg_base(void);</span><br><span> int cpu_get_apic_id_map(int *apic_id_map);</span><br><span> void northbridge_write_smram(u8 smram);</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,</span><br><span style="color: hsl(0, 100%, 40%);">- size_t *smm_save_state_size);</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_initialize(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_smm_clear_state(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t staggered_smbase);</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_relocate(void);</span><br><span>diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>index 4fccd2d..e80fa31 100644</span><br><span>--- a/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>+++ b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>@@ -23,12 +23,10 @@</span><br><span> #include <device/pci.h></span><br><span> #include <cpu/cpu.h></span><br><span> #include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/mp.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/x86/smm.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <smp/node.h></span><br><span> #include "smi.h"</span><br><span> </span><br><span> #define SMRR_SUPPORTED (1 << 11)</span><br><span>@@ -294,78 +292,3 @@</span><br><span> </span><br><span> northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,</span><br><span style="color: hsl(0, 100%, 40%);">- size_t *smm_save_state_size)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Setting up SMI for CPU\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- fill_in_relocation_params(&smm_reloc_params);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- setup_ied_area(&smm_reloc_params);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- *perm_smbase = smm_reloc_params.smram_base;</span><br><span style="color: hsl(0, 100%, 40%);">- *perm_smsize = smm_reloc_params.smram_size;</span><br><span style="color: hsl(0, 100%, 40%);">- *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_initialize(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear the SMM state in the southbridge. */</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smm_clear_state();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Run the relocation handler for on the BSP to check and set up</span><br><span style="color: hsl(0, 100%, 40%);">- * parallel SMM relocation.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- smm_initiate_relocation();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* The relocation work is actually performed in SMM context, but the code</span><br><span style="color: hsl(0, 100%, 40%);">- * resides in the ramstage module. This occurs by trampolining from the default</span><br><span style="color: hsl(0, 100%, 40%);">- * SMRAM entry point to here. */</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t staggered_smbase)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t mtrr_cap;</span><br><span style="color: hsl(0, 100%, 40%);">- struct smm_relocation_params *relo_params = &smm_reloc_params;</span><br><span style="color: hsl(0, 100%, 40%);">- em64t101_smm_state_save_area_t *save_state;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 smbase = staggered_smbase;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 iedbase = relo_params->ied_base;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Make appropriate changes to the save state map. */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- smbase, iedbase);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(*save_state));</span><br><span style="color: hsl(0, 100%, 40%);">- save_state->smbase = smbase;</span><br><span style="color: hsl(0, 100%, 40%);">- save_state->iedbase = iedbase;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write EMRR and SMRR MSRs based on indicated support. */</span><br><span style="color: hsl(0, 100%, 40%);">- mtrr_cap = rdmsr(MTRR_CAP_MSR);</span><br><span style="color: hsl(0, 100%, 40%);">- if (mtrr_cap.lo & SMRR_SUPPORTED && !IS_ENABLED(CONFIG_HAS_NO_SMRR))</span><br><span style="color: hsl(0, 100%, 40%);">- write_smrr(relo_params);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * The default SMM entry can happen in parallel or serially. If the</span><br><span style="color: hsl(0, 100%, 40%);">- * default SMM entry is done in parallel the BSP has already setup</span><br><span style="color: hsl(0, 100%, 40%);">- * the saving state to each CPU's MSRs. At least one save state size</span><br><span style="color: hsl(0, 100%, 40%);">- * is required for the initial SMM entry for the BSP to determine if</span><br><span style="color: hsl(0, 100%, 40%);">- * parallel SMM relocation is even feasible.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_relocate(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * If smm_save_state_in_msrs is non-zero then parallel SMM relocation</span><br><span style="color: hsl(0, 100%, 40%);">- * shall take place. Run the relocation handler a second time on the</span><br><span style="color: hsl(0, 100%, 40%);">- * BSP to do * the final move. For APs, a relocation handler always</span><br><span style="color: hsl(0, 100%, 40%);">- * needs to be run.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!boot_cpu())</span><br><span style="color: hsl(0, 100%, 40%);">- smm_initiate_relocation();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c</span><br><span>index 2258067..9fed17e 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/northbridge.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/northbridge.c</span><br><span>@@ -525,7 +525,7 @@</span><br><span> </span><br><span> static void cpu_bus_init(device_t dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- bsp_init_and_start_aps(dev->link_list);</span><br><span style="color: hsl(120, 100%, 40%);">+ initialize_cpus(dev->link_list);</span><br><span> }</span><br><span> </span><br><span> static struct device_operations cpu_bus_ops = {</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c</span><br><span>index 96098fa..814ff80 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/elog.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/elog.c</span><br><span>@@ -22,7 +22,7 @@</span><br><span> #include <stdint.h></span><br><span> #include <string.h></span><br><span> #include <elog.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/pmutils.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "pch.h"</span><br><span> </span><br><span> void pch_log_state(void)</span><br><span> {</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>index 9e87ff6..ebcb058 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>@@ -68,6 +68,9 @@</span><br><span> int pch_silicon_type(void);</span><br><span> int pch_silicon_supported(int type, int rev);</span><br><span> void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_ELOG)</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_log_state(void);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> #else /* __PRE_RAM__ */</span><br><span> void enable_smbus(void);</span><br><span> void enable_usb_bar(void);</span><br><span>diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h</span><br><span>index 4aa2812..e2b6e58 100644</span><br><span>--- a/src/southbridge/intel/common/pmutil.h</span><br><span>+++ b/src/southbridge/intel/common/pmutil.h</span><br><span>@@ -123,6 +123,5 @@</span><br><span> void southbridge_finalize_all(void);</span><br><span> void southbridge_smi_monitor(void);</span><br><span> em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd);</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_log_state(void);</span><br><span> </span><br><span> #endif /*INTEL_COMMON_PMUTIL_H */</span><br><span>diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c</span><br><span>index 264b548..deaecb2 100644</span><br><span>--- a/src/southbridge/intel/common/smi.c</span><br><span>+++ b/src/southbridge/intel/common/smi.c</span><br><span>@@ -159,29 +159,3 @@</span><br><span> "d" (APM_CNT)</span><br><span> );</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_smm_clear_state(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 smi_en;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_ELOG))</span><br><span style="color: hsl(0, 100%, 40%);">- /* Log events from chipset before clearing */</span><br><span style="color: hsl(0, 100%, 40%);">- pch_log_state();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Initializing Southbridge SMI...");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en = inl(get_pmbase() + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_en & APMC_EN) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "SMI# handler already enabled?\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Dump and clear status registers */</span><br><span style="color: hsl(0, 100%, 40%);">- reset_smi_status();</span><br><span style="color: hsl(0, 100%, 40%);">- reset_pm1_status();</span><br><span style="color: hsl(0, 100%, 40%);">- reset_tco_status();</span><br><span style="color: hsl(0, 100%, 40%);">- reset_gpe0_status();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25616">change 25616</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I87497093ccf6909b88e3a40d5f472afeb7f2c552 </div>
<div style="display:none"> Gerrit-Change-Number: 25616 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>