<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25586">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl1: Make DRAM configuration more flexible<br><br>By storing the FSP-M DRAM configuration parameter in the hwinfo block,<br>one becomes more flexible in case of a change of the DRAM type.<br>The configuration data from hwinfo block is a one-to-one representation<br>of the FSPM_UPD data starting with parameter 'Package' (offset 0x4d) and<br>ending before parameter 'Ch0_Bit_swizzling' (offset 0x88).<br><br>Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/romstage.c<br>1 file changed, 27 insertions(+), 56 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/25586/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c</span><br><span>index 3462c76..24d03b6 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/romstage.c</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/romstage.c</span><br><span>@@ -14,6 +14,9 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <hwilib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <lib.h></span><br><span> #include <string.h></span><br><span> #include <soc/romstage.h></span><br><span> #include <fsp/api.h></span><br><span>@@ -48,67 +51,34 @@</span><br><span> void mainboard_memory_init_params(FSPM_UPD *memupd)</span><br><span> {</span><br><span> const struct pad_config *pads;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t spd[0x80];</span><br><span> size_t num;</span><br><span> </span><br><span> /* setup early gpio before memory */</span><br><span> pads = brd_early_gpio_table(&num);</span><br><span> gpio_configure_pads(pads, num);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* DRAM Config settings */</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Package = 0x1;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Profile = 0x19;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.MemoryDown = 0x5;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.DDR3LPageSize = 0x2;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.DDR3LASR = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.ScramblerSupport = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.ChannelHashMask = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.SliceHashMask = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.InterleavedMode = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.ChannelsSlicesEnable = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.MinRefRate2xEnable = 0x1;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.DualRankSupportEnable = 0x1;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.RmtMode = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.MemorySizeLimit = 0x1000;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.LowMemoryMaxValue = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.DisableFastBoot = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.HighMemoryMaxValue = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.DIMM0SPDAddress = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.DIMM1SPDAddress = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch0_RankEnable = 0x1;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch0_DeviceWidth = 0x1;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch0_DramDensity = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch0_Option = 0x3;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch0_OdtConfig = 0x1;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch0_TristateClk1 = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch0_Mode2N = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch0_OdtLevels = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch1_RankEnable = 0x1;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch1_DeviceWidth = 0x1;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch1_DramDensity = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch1_Option = 0x3;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch1_OdtConfig = 0x1;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch1_TristateClk1 = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch1_Mode2N = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch1_OdtLevels = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch2_RankEnable = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch2_DeviceWidth = 0x1;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch2_DramDensity = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch2_Option = 0x3;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch2_OdtConfig = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch2_TristateClk1 = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch2_Mode2N = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch2_OdtLevels = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch3_RankEnable = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch3_DeviceWidth = 0x1;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch3_DramDensity = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch3_Option = 0x3;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch3_OdtConfig = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch3_TristateClk1 = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch3_Mode2N = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.Ch3_OdtLevels = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.RmtCheckRun = 0x3;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.MrcDataSaving = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.MrcFastBoot = 0x1;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get DRAM configuration data from hwinfo block.</span><br><span style="color: hsl(120, 100%, 40%);">+ * The configuration data from hwinfo block is a one-to-one</span><br><span style="color: hsl(120, 100%, 40%);">+ * representation of the FSPM_UPD data starting with parameter</span><br><span style="color: hsl(120, 100%, 40%);">+ * 'Package' (offset 0x4d) and ending before parameter</span><br><span style="color: hsl(120, 100%, 40%);">+ * 'Ch0_Bit_swizzling' (offset 0x88).</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hwilib_find_blocks("hwinfo.hex")) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR,</span><br><span style="color: hsl(120, 100%, 40%);">+ "HWInfo not found, use default values for FSP-M.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hwilib_get_field(SPD, spd, sizeof(spd)) != sizeof(spd)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR,</span><br><span style="color: hsl(120, 100%, 40%);">+ "SPD not found in HWInfo, use defaults for FSP-M.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Package, &spd,</span><br><span style="color: hsl(120, 100%, 40%);">+ (((uint8_t *)memupd->FspmConfig.Ch0_Bit_swizzling)-</span><br><span style="color: hsl(120, 100%, 40%);">+ (&memupd->FspmConfig.Package)));</span><br><span> </span><br><span> memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling,</span><br><span> sizeof(Ch0_Bit_swizzling));</span><br><span>@@ -119,6 +89,7 @@</span><br><span> memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling,</span><br><span> sizeof(Ch3_Bit_swizzling));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8;</span><br><span> memupd->FspmConfig.MsgLevelMask = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ memupd->FspmConfig.MrcDataSaving = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ memupd->FspmConfig.MrcFastBoot = 0x1;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25586">change 25586</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25586"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6 </div>
<div style="display:none"> Gerrit-Change-Number: 25586 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>