<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25606">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/x4x: Put stage cache in TSEG<br><br>TSEG is not accessible in ring 0 after it is locked in ramstage, in<br>contrast with cbmem which remains accessible. Assuming SMM does not<br>touch the cache this is a good region to cache stages.<br><br>Untested.<br><br>Change-Id: Ie46c1416f8042d5571339b36e1253c0cae0684b8<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/x4x/Kconfig<br>M src/northbridge/intel/x4x/Makefile.inc<br>A src/northbridge/intel/x4x/stage_cache.c<br>3 files changed, 51 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/25606/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig</span><br><span>index 0e1a20f..bd06f08 100644</span><br><span>--- a/src/northbridge/intel/x4x/Kconfig</span><br><span>+++ b/src/northbridge/intel/x4x/Kconfig</span><br><span>@@ -30,6 +30,7 @@</span><br><span> select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span> select SMM_TSEG</span><br><span> select PARALLEL_MP</span><br><span style="color: hsl(120, 100%, 40%);">+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</span><br><span> </span><br><span> config CBFS_SIZE</span><br><span> hex</span><br><span>@@ -47,4 +48,13 @@</span><br><span> hex</span><br><span> default 0xe0000000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config SMM_RESERVED_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x100000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# Intel Enhanced Debug region must be 4MB</span><br><span style="color: hsl(120, 100%, 40%);">+config IED_REGION_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x400000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc</span><br><span>index 5c64ca7..10a6d71 100644</span><br><span>--- a/src/northbridge/intel/x4x/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/x4x/Makefile.inc</span><br><span>@@ -27,4 +27,7 @@</span><br><span> ramstage-y += gma.c</span><br><span> ramstage-y += northbridge.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/x4x/stage_cache.c b/src/northbridge/intel/x4x/stage_cache.c</span><br><span>new file mode 100644</span><br><span>index 0000000..8ac3171</span><br><span>--- /dev/null</span><br><span>+++ b/src/northbridge/intel/x4x/stage_cache.c</span><br><span>@@ -0,0 +1,38 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2015 Google, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stage_cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "x4x.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void stage_cache_external_region(void **base, size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.</span><br><span style="color: hsl(120, 100%, 40%);">+ * The top of RAM is defined to be the TSEG base address.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = CONFIG_SMM_RESERVED_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 esmramc = pci_read_config8(PCI_DEV(0, 0x00, 0), D0F0_ESMRAMC);</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)),</span><br><span style="color: hsl(120, 100%, 40%);">+ D0F0_ESMRAMC);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 tseg_size = decode_tseg_size(esmramc);</span><br><span style="color: hsl(120, 100%, 40%);">+ *base = (void *)((uintptr_t)cbmem_top() + tseg_size</span><br><span style="color: hsl(120, 100%, 40%);">+ - CONFIG_SMM_RESERVED_SIZE - CONFIG_IED_REGION_SIZE);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25606">change 25606</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie46c1416f8042d5571339b36e1253c0cae0684b8 </div>
<div style="display:none"> Gerrit-Change-Number: 25606 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>