<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25594">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/i82801gx: Use common Intel SMM code<br><br>Untested<br><br>Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/southbridge/intel/common/pmutil.h<br>M src/southbridge/intel/i82801gx/Kconfig<br>M src/southbridge/intel/i82801gx/i82801gx.h<br>M src/southbridge/intel/i82801gx/smi.c<br>M src/southbridge/intel/i82801gx/smihandler.c<br>5 files changed, 18 insertions(+), 877 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/25594/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h</span><br><span>index 4aa2812..d8292b7 100644</span><br><span>--- a/src/southbridge/intel/common/pmutil.h</span><br><span>+++ b/src/southbridge/intel/common/pmutil.h</span><br><span>@@ -58,8 +58,14 @@</span><br><span> #define LV2 0x14</span><br><span> #define LV3 0x15</span><br><span> #define LV4 0x16</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM2_CNT 0x20 // mobile only</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_STS 0x28</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span> #define PM2_CNT 0x50 // mobile only</span><br><span> #define GPE0_STS 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB4_STS (1 << 14) /* i82801gx only */</span><br><span> #define PME_B0_STS (1 << 13)</span><br><span> #define PME_STS (1 << 11)</span><br><span> #define BATLOW_STS (1 << 10)</span><br><span>@@ -69,7 +75,11 @@</span><br><span> #define TCOSCI_STS (1 << 6)</span><br><span> #define SWGPE_STS (1 << 2)</span><br><span> #define HOT_PLUG_STS (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_EN 0x2c</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span> #define GPE0_EN 0x28</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) */</span><br><span> #define PME_B0_EN (1 << 13)</span><br><span> #define PME_EN (1 << 11)</span><br><span> #define TCOSCI_EN (1 << 6)</span><br><span>diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig</span><br><span>index 9fd19ed..e2beacd 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/Kconfig</span><br><span>+++ b/src/southbridge/intel/i82801gx/Kconfig</span><br><span>@@ -26,6 +26,7 @@</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_GPIO</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SMBUS</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_COMMON_SMM</span><br><span> </span><br><span> if SOUTHBRIDGE_INTEL_I82801GX</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>index df744fc..e82f54d 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>+++ b/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>@@ -46,7 +46,6 @@</span><br><span> #if !defined(__SIMPLE_DEVICE__)</span><br><span> void i82801gx_enable(device_t dev);</span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">-void gpi_route_interrupt(u8 gpi, u8 mode);</span><br><span> #else</span><br><span> void enable_smbus(void);</span><br><span> int smbus_read_byte(unsigned int device, unsigned int address);</span><br><span>diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c</span><br><span>index 7355d11..d94862d 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/smi.c</span><br><span>+++ b/src/southbridge/intel/i82801gx/smi.c</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #include <cpu/x86/cache.h></span><br><span> #include <cpu/x86/smm.h></span><br><span> #include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/pmutil.h></span><br><span> #include "i82801gx.h"</span><br><span> </span><br><span> /* I945 */</span><br><span>@@ -39,253 +40,6 @@</span><br><span> */</span><br><span> static u16 pmbase = DEFAULT_PMBASE;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear PM1_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return PM1_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 reset_pm1_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = inw(pmbase + PM1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outw(reg16, pmbase + PM1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_pm1_status(u16 pm1_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PM1_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 15))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "WAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 14))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PCIEXPWAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 11))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PRBTNOR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 10))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "RTC ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 8))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PWRBTN ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 5))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GBL ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 4))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "BM ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 0))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TMROF ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return SMI_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_smi_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_smi_status(u32 smi_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 26))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SPI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 25))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "EL_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 21))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MONITOR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 20))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PCI_EXP_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 18))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "INTEL_USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 17))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "LEGACY_USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 16))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMBUS_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 15))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SERIRQ_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 14))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PERIODIC ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 13))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 12))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "DEVMON ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 11))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MCSMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 10))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 9))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPE0 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 8))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PM1 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 6))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SWSMI_TMR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 5))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "APM ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 4))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SLP_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 3))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "LEGACY_USB ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 2))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "BIOS ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear GPE0_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return GPE0_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_gpe0_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + GPE0_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + GPE0_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_gpe0_status(u32 gpe0_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPE0_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 31; i >= 16; i--) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << i))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPIO%d ", (i-16));</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 14))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "USB4 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 13))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PME_B0 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 12))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "USB3 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 11))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PME ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 10))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "EL_SCI/BATLOW ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 9))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PCI_EXP ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 8))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "RI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 7))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMB_WAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 6))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO_SCI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 5))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "AC97 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 4))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 3))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "USB1 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 2))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "HOT_PLUG ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 0))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "THRM ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear ALT_GP_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return ALT_GP_SMI_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 reset_alt_gp_smi_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = inl(pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg16, pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 15; i >= 0; i--) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (alt_gp_smi_sts & (1 << i))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPI%d ", i);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear TCOx_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return TCOx_STS registers</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_tco_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 tcobase = pmbase + 0x60;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(tcobase + 0x04);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & (1 << 18))</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_tco_status(u32 tco_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 20))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMLINK_SLV ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 18))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "BOOT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 17))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SECOND_TO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 16))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "INTRD_DET ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 12))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "DMISERR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 10))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "DMISMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 9))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "DMISCI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 8))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "BIOSWR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 7))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "NEWCENTURY ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 3))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TIMEOUT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 2))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO_INT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 1))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SW_TCO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 0))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "NMI2SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief Set the EOS bit</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void smi_set_eos(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = inb(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= EOS;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(reg8, pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> extern uint8_t smm_relocation_start, smm_relocation_end;</span><br><span> static void *default_smm_area = NULL;</span><br><span> </span><br><span>@@ -430,12 +184,3 @@</span><br><span> pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,</span><br><span> D_LCK | G_SMRAME | C_BASE_SEG);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* The GDT or coreboot table is going to live here. But a long time</span><br><span style="color: hsl(0, 100%, 40%);">- * after we relocated the GNVS, so this is not troublesome.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- *(u32 *)0x500 = (u32)gnvs;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0xea, 0xb2);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c</span><br><span>index 3f537c0..1b4a063 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/smihandler.c</span><br><span>+++ b/src/southbridge/intel/i82801gx/smihandler.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <device/pci_def.h></span><br><span> #include <halt.h></span><br><span> #include <pc80/mc146818rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/pmutil.h></span><br><span> #include "i82801gx.h"</span><br><span> </span><br><span> /* I945 */</span><br><span>@@ -45,246 +46,10 @@</span><br><span> */</span><br><span> global_nvs_t *gnvs = (global_nvs_t *)0x0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void alt_gpi_mask(u16 clr, u16 set)</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- alt_gp &= ~clr;</span><br><span style="color: hsl(0, 100%, 40%);">- alt_gp |= set;</span><br><span style="color: hsl(0, 100%, 40%);">- outw(alt_gp, pmbase + ALT_GP_SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void gpe0_mask(u32 clr, u32 set)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpe0 = inl(pmbase + GPE0_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- gpe0 &= ~clr;</span><br><span style="color: hsl(0, 100%, 40%);">- gpe0 |= set;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(gpe0, pmbase + GPE0_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void gpi_route_interrupt(u8 gpi, u8 mode)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpi_rout;</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpi >= 16)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- alt_gpi_mask(1 << gpi, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- gpe0_mask(1 << (gpi+16), 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);</span><br><span style="color: hsl(0, 100%, 40%);">- gpi_rout &= ~(3 << (2 * gpi));</span><br><span style="color: hsl(0, 100%, 40%);">- gpi_rout |= ((mode & 3) << (2 * gpi));</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (mode == GPI_IS_SCI)</span><br><span style="color: hsl(0, 100%, 40%);">- gpe0_mask(0, 1 << (gpi+16));</span><br><span style="color: hsl(0, 100%, 40%);">- else if (mode == GPI_IS_SMI)</span><br><span style="color: hsl(0, 100%, 40%);">- alt_gpi_mask(0, 1 << gpi);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear PM1_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return PM1_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 reset_pm1_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = inw(pmbase + PM1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outw(reg16, pmbase + PM1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_pm1_status(u16 pm1_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "PM1_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 15))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "WAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 14))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "PCIEXPWAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 11))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "PRBTNOR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 10))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "RTC ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 8))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "PWRBTN ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 5))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "GBL ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 4))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "BM ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 0))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "TMROF ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">- int reg16 = inw(pmbase + PM1_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return SMI_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_smi_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_smi_status(u32 smi_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 26))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SPI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 25))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "EL_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 21))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MONITOR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 20))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PCI_EXP_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 18))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "INTEL_USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 17))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "LEGACY_USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 16))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMBUS_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 15))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SERIRQ_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 14))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PERIODIC ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 13))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 12))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "DEVMON ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 11))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MCSMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 10))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 9))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPE0 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 8))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PM1 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 6))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SWSMI_TMR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 5))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "APM ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 4))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SLP_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 3))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "LEGACY_USB ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 2))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "BIOS ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear GPE0_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return GPE0_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_gpe0_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + GPE0_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + GPE0_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_gpe0_status(u32 gpe0_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPE0_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 31; i >= 16; i--) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << i))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPIO%d ", (i-16));</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 14))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "USB4 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 13))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PME_B0 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 12))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "USB3 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 11))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PME ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 10))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "EL_SCI/BATLOW ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 9))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PCI_EXP ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 8))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "RI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 7))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMB_WAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 6))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO_SCI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 5))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "AC97 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 4))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 3))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "USB1 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 2))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "HOT_PLUG ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 0))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "THRM ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear TCOx_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return TCOx_STS registers</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_tco_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 tcobase = pmbase + 0x60;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(tcobase + 0x04);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & (1 << 18))</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_tco_status(u32 tco_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 20))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMLINK_SLV ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 18))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "BOOT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 17))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SECOND_TO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 16))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "INTRD_DET ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 12))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "DMISERR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 10))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "DMISMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 9))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "DMISCI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 8))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "BIOSWR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 7))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "NEWCENTURY ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 3))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TIMEOUT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 2))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO_INT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 1))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SW_TCO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 0))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "NMI2SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs = *(global_nvs_t **)0x500;</span><br><span style="color: hsl(120, 100%, 40%);">+ *smm_done = 1;</span><br><span> }</span><br><span> </span><br><span> int southbridge_io_trap_handler(int smif)</span><br><span>@@ -304,312 +69,7 @@</span><br><span> return 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief Set the EOS bit</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_smi_set_eos(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = inb(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= EOS;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(reg8, pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void busmaster_disable_on_bus(int bus)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int slot, func;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int val;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char hdr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (slot = 0; slot < 0x20; slot++) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (func = 0; func < 8; func++) {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_devfn_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- val = pci_read_config32(dev, PCI_VENDOR_ID);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (val == 0xffffffff || val == 0x00000000 ||</span><br><span style="color: hsl(0, 100%, 40%);">- val == 0x0000ffff || val == 0xffff0000)</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable Bus Mastering for this one device */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = pci_read_config32(dev, PCI_COMMAND);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= ~PCI_COMMAND_MASTER;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* If this is a bridge, then follow it. */</span><br><span style="color: hsl(0, 100%, 40%);">- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);</span><br><span style="color: hsl(0, 100%, 40%);">- hdr &= 0x7f;</span><br><span style="color: hsl(0, 100%, 40%);">- if (hdr == PCI_HEADER_TYPE_BRIDGE ||</span><br><span style="color: hsl(0, 100%, 40%);">- hdr == PCI_HEADER_TYPE_CARDBUS) {</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int buses;</span><br><span style="color: hsl(0, 100%, 40%);">- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);</span><br><span style="color: hsl(0, 100%, 40%);">- busmaster_disable_on_bus((buses >> 8) & 0xff);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 slp_typ;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // save and recover RTC port values</span><br><span style="color: hsl(0, 100%, 40%);">- u8 tmp70, tmp72;</span><br><span style="color: hsl(0, 100%, 40%);">- tmp70 = inb(0x70);</span><br><span style="color: hsl(0, 100%, 40%);">- tmp72 = inb(0x72);</span><br><span style="color: hsl(0, 100%, 40%);">- get_option(&s5pwr, "power_on_after_fail");</span><br><span style="color: hsl(0, 100%, 40%);">- outb(tmp70, 0x70);</span><br><span style="color: hsl(0, 100%, 40%);">- outb(tmp72, 0x72);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* First, disable further SMIs */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = inb(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 &= ~SLP_SMI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(reg8, pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Figure out SLP_TYP */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);</span><br><span style="color: hsl(0, 100%, 40%);">- slp_typ = acpi_sleep_from_pm1(reg32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Next, do the deed.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- switch (slp_typ) {</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S0:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S1:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S3:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");</span><br><span style="color: hsl(0, 100%, 40%);">- /* Invalidate the cache before going to S3 */</span><br><span style="color: hsl(0, 100%, 40%);">- wbinvd();</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S4:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;</span><br><span style="color: hsl(0, 100%, 40%);">- case ACPI_S5:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- outl(0, pmbase + GPE0_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Always set the flag in case CMOS was changed on runtime. For</span><br><span style="color: hsl(0, 100%, 40%);">- * "KEEP", switch to "OFF" - KEEP is software emulated</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);</span><br><span style="color: hsl(0, 100%, 40%);">- if (s5pwr == MAINBOARD_POWER_ON)</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 &= ~1;</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= 1;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* also iterates over all bridges on bus 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- busmaster_disable_on_bus(0);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- default:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if !IS_ENABLED(CONFIG_SMM_TSEG)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Unlock the SMI semaphore. We're currently in SMM, and the semaphore</span><br><span style="color: hsl(0, 100%, 40%);">- * will never be unlocked because the next outl will switch off the CPU.</span><br><span style="color: hsl(0, 100%, 40%);">- * This might open a small race between the smi_release_lock() and the outl()</span><br><span style="color: hsl(0, 100%, 40%);">- * for other SMI handlers. Not sure if this could cause trouble. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (slp_typ == ACPI_S3)</span><br><span style="color: hsl(0, 100%, 40%);">- smi_release_lock();</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write back to the SLP register to cause the originally intended</span><br><span style="color: hsl(0, 100%, 40%);">- * event again. We need to set BIT13 (SLP_EN) though to make the</span><br><span style="color: hsl(0, 100%, 40%);">- * sleep happen.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 | SLP_EN, pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Make sure to stop executing code here for S3/S4/S5 */</span><br><span style="color: hsl(0, 100%, 40%);">- if (slp_typ >= ACPI_S3)</span><br><span style="color: hsl(0, 100%, 40%);">- halt();</span><br><span style="color: hsl(0, 100%, 40%);">- /* In most sleep states, the code flow of this function ends at</span><br><span style="color: hsl(0, 100%, 40%);">- * the line above. However, if we entered sleep state S1 and wake</span><br><span style="color: hsl(0, 100%, 40%);">- * up again, we will continue to execute code in this function.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & SCI_EN) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* The OS is not an ACPI OS, so we set the state to S0 */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= ~(SLP_EN | SLP_TYP);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pmctrl;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Emulate B2 register as the FADT / Linux expects it */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = inb(APM_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- if (mainboard_smi_apmc(reg8))</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- switch (reg8) {</span><br><span style="color: hsl(0, 100%, 40%);">- case APM_CNT_CST_CONTROL:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Calling this function seems to cause</span><br><span style="color: hsl(0, 100%, 40%);">- * some kind of race condition in Linux</span><br><span style="color: hsl(0, 100%, 40%);">- * and causes a kernel oops</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "C-state control\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case APM_CNT_PST_CONTROL:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Calling this function seems to cause</span><br><span style="color: hsl(0, 100%, 40%);">- * some kind of race condition in Linux</span><br><span style="color: hsl(0, 100%, 40%);">- * and causes a kernel oops</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "P-state control\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case APM_CNT_ACPI_DISABLE:</span><br><span style="color: hsl(0, 100%, 40%);">- pmctrl = inl(pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- pmctrl &= ~SCI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(pmctrl, pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case APM_CNT_ACPI_ENABLE:</span><br><span style="color: hsl(0, 100%, 40%);">- pmctrl = inl(pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- pmctrl |= SCI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(pmctrl, pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case APM_CNT_GNVS_UPDATE:</span><br><span style="color: hsl(0, 100%, 40%);">- if (smm_initialized) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- gnvs = *(global_nvs_t **)0x500;</span><br><span style="color: hsl(0, 100%, 40%);">- smm_initialized = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: Setting up structures to %p\n", gnvs);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- default:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 pm1_sts;</span><br><span style="color: hsl(0, 100%, 40%);">- volatile u8 cmos_status;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pm1_sts = reset_pm1_status();</span><br><span style="color: hsl(0, 100%, 40%);">- dump_pm1_status(pm1_sts);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* While OSPM is not active, poweroff immediately</span><br><span style="color: hsl(0, 100%, 40%);">- * on a power button event.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & PWRBTN_STS) {</span><br><span style="color: hsl(0, 100%, 40%);">- // power button pressed</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = (7 << 10) | (1 << 13);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & RTC_STS) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* read RTC status register to disable the interrupt */</span><br><span style="color: hsl(0, 100%, 40%);">- cmos_status = cmos_read(RTC_REG_C);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "RTC IRQ status: %02X\n", cmos_status);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpe0_sts;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- gpe0_sts = reset_gpe0_status();</span><br><span style="color: hsl(0, 100%, 40%);">- dump_gpe0_status(gpe0_sts);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = inw(pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- outw(reg16, pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 &= inw(pmbase + ALT_GP_SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_smi_gpi(reg16);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg16)</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Are periodic SMIs enabled? */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((reg32 & MCSMI_EN) == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Microcontroller SMI.\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 tco_sts;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- tco_sts = reset_tco_status();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Any TCO event? */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!tco_sts)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 8)) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* BIOSWR */</span><br><span style="color: hsl(0, 100%, 40%);">- u8 bios_cntl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (bios_cntl & 1) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* BWE is RW, so the SMI was caused by a</span><br><span style="color: hsl(0, 100%, 40%);">- * write to BWE, not by a write to the BIOS</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* This is the place where we notice someone</span><br><span style="color: hsl(0, 100%, 40%);">- * is trying to tinker with the BIOS. We are</span><br><span style="color: hsl(0, 100%, 40%);">- * trying to be nice and just ignore it. A more</span><br><span style="color: hsl(0, 100%, 40%);">- * resolute answer would be to power down the</span><br><span style="color: hsl(0, 100%, 40%);">- * box.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Switching back to RO\n");</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));</span><br><span style="color: hsl(0, 100%, 40%);">- } /* No else for now? */</span><br><span style="color: hsl(0, 100%, 40%);">- } else if (tco_sts & (1 << 3)) { /* TIMEOUT */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Handle TCO timeout */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO Timeout.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- } else if (!tco_sts) {</span><br><span style="color: hsl(0, 100%, 40%);">- dump_tco_status(tco_sts);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Are periodic SMIs enabled? */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((reg32 & PERIODIC_EN) == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Periodic SMI.\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_smi_monitor(void)</span><br><span> {</span><br><span> #define IOTRAP(x) (trap_sts & (1 << x))</span><br><span> u32 trap_sts, trap_cycle;</span><br><span>@@ -654,80 +114,6 @@</span><br><span> #undef IOTRAP</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-typedef void (*smi_handler_t)(unsigned int node,</span><br><span style="color: hsl(0, 100%, 40%);">- smm_state_save_area_t *state_save);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-smi_handler_t southbridge_smi[32] = {</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [0] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [1] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [2] BIOS_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [3] LEGACY_USB_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_sleep, // [4] SLP_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_apmc, // [5] APM_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [6] SWSMI_TMR_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [7] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_pm1, // [8] PM1_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_gpe0, // [9] GPE0_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_gpi, // [10] GPI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_mc, // [11] MCSMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [12] DEVMON_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_tco, // [13] TCO_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_periodic, // [14] PERIODIC_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [15] SERIRQ_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [16] SMBUS_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [17] LEGACY_USB2_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [18] INTEL_USB2_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [19] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [20] PCI_EXP_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi_monitor, // [21] MONITOR_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [22] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [23] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [24] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [25] EL_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [26] SPI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [27] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [28] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [29] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL, // [30] reserved</span><br><span style="color: hsl(0, 100%, 40%);">- NULL // [31] reserved</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief Interrupt handler for SMI#</span><br><span style="color: hsl(0, 100%, 40%);">- * @param node</span><br><span style="color: hsl(0, 100%, 40%);">- * @param state_save</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_finalize_all(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- int i, dump = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 smi_sts;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Update global variable pmbase */</span><br><span style="color: hsl(0, 100%, 40%);">- pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* We need to clear the SMI status registers, or we won't see what's</span><br><span style="color: hsl(0, 100%, 40%);">- * happening in the following calls.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_sts = reset_smi_status();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Filter all non-enabled SMI events */</span><br><span style="color: hsl(0, 100%, 40%);">- // FIXME Double check, this clears MONITOR</span><br><span style="color: hsl(0, 100%, 40%);">- // smi_sts &= inl(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Call SMI sub handler for each of the status bits */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 31; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << i)) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (southbridge_smi[i])</span><br><span style="color: hsl(0, 100%, 40%);">- southbridge_smi[i](node, state_save);</span><br><span style="color: hsl(0, 100%, 40%);">- else {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "</span><br><span style="color: hsl(0, 100%, 40%);">- "handler available.\n", i);</span><br><span style="color: hsl(0, 100%, 40%);">- dump = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (dump)</span><br><span style="color: hsl(0, 100%, 40%);">- dump_smi_status(smi_sts);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25594">change 25594</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25594"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0 </div>
<div style="display:none"> Gerrit-Change-Number: 25594 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>