<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25600">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/i945: Use parallel MP init<br><br>untested<br><br>Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/model_106cx/Makefile.inc<br>M src/cpu/intel/model_106cx/model_106cx_init.c<br>M src/cpu/intel/model_6ex/Makefile.inc<br>M src/cpu/intel/model_6ex/model_6ex_init.c<br>M src/cpu/intel/model_f3x/Makefile.inc<br>M src/cpu/intel/model_f3x/model_f3x_init.c<br>M src/cpu/intel/model_f4x/Makefile.inc<br>M src/cpu/intel/model_f4x/model_f4x_init.c<br>M src/northbridge/intel/i945/Kconfig<br>M src/northbridge/intel/i945/northbridge.c<br>10 files changed, 20 insertions(+), 39 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/25600/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc</span><br><span>index 0703099..eec544d 100644</span><br><span>--- a/src/cpu/intel/model_106cx/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_106cx/Makefile.inc</span><br><span>@@ -2,5 +2,6 @@</span><br><span> subdirs-y += ../../x86/name</span><br><span> subdirs-y += ../common</span><br><span> subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin</span><br><span>diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c</span><br><span>index dd7bbc8..5ea39a9 100644</span><br><span>--- a/src/cpu/intel/model_106cx/model_106cx_init.c</span><br><span>+++ b/src/cpu/intel/model_106cx/model_106cx_init.c</span><br><span>@@ -86,15 +86,18 @@</span><br><span> x86_enable_cache();</span><br><span> </span><br><span> /* Update the microcode */</span><br><span style="color: hsl(0, 100%, 40%);">- intel_update_microcode_from_cbfs();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_PARALLEL_MP))</span><br><span style="color: hsl(120, 100%, 40%);">+ intel_update_microcode_from_cbfs();</span><br><span> </span><br><span> /* Print processor name */</span><br><span> fill_processor_name(processor_name);</span><br><span> printk(BIOS_INFO, "CPU: %s.\n", processor_name);</span><br><span> </span><br><span> /* Setup MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- x86_setup_mtrrs();</span><br><span style="color: hsl(0, 100%, 40%);">- x86_mtrr_check();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_PARALLEL_MP)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ x86_setup_mtrrs();</span><br><span style="color: hsl(120, 100%, 40%);">+ x86_mtrr_check();</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> /* Enable the local CPU APICs */</span><br><span> setup_lapic();</span><br><span>@@ -111,7 +114,8 @@</span><br><span> /* TODO: PIC thermal sensor control */</span><br><span> </span><br><span> /* Start up my CPU siblings */</span><br><span style="color: hsl(0, 100%, 40%);">- intel_sibling_init(cpu);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_PARALLEL_MP))</span><br><span style="color: hsl(120, 100%, 40%);">+ intel_sibling_init(cpu);</span><br><span> }</span><br><span> </span><br><span> static struct device_operations cpu_dev_ops = {</span><br><span>diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc</span><br><span>index 13e08f0..46ae7c7 100644</span><br><span>--- a/src/cpu/intel/model_6ex/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_6ex/Makefile.inc</span><br><span>@@ -2,5 +2,6 @@</span><br><span> subdirs-y += ../../x86/name</span><br><span> subdirs-y += ../common</span><br><span> subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += ../model_1067x/mp_init.c</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin</span><br><span>diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c</span><br><span>index 96830c4..a6daf17 100644</span><br><span>--- a/src/cpu/intel/model_6ex/model_6ex_init.c</span><br><span>+++ b/src/cpu/intel/model_6ex/model_6ex_init.c</span><br><span>@@ -119,17 +119,10 @@</span><br><span> /* Turn on caching if we haven't already */</span><br><span> x86_enable_cache();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Update the microcode */</span><br><span style="color: hsl(0, 100%, 40%);">- intel_update_microcode_from_cbfs();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Print processor name */</span><br><span> fill_processor_name(processor_name);</span><br><span> printk(BIOS_INFO, "CPU: %s.\n", processor_name);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- x86_setup_mtrrs();</span><br><span style="color: hsl(0, 100%, 40%);">- x86_mtrr_check();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Setup Page Attribute Tables (PAT) */</span><br><span> // TODO set up PAT</span><br><span> </span><br><span>@@ -147,9 +140,6 @@</span><br><span> </span><br><span> /* PIC thermal sensor control */</span><br><span> configure_pic_thermal_sensors();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Start up my CPU siblings */</span><br><span style="color: hsl(0, 100%, 40%);">- intel_sibling_init(cpu);</span><br><span> }</span><br><span> </span><br><span> static struct device_operations cpu_dev_ops = {</span><br><span>diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc</span><br><span>index 7367914..19b2e93 100644</span><br><span>--- a/src/cpu/intel/model_f3x/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_f3x/Makefile.inc</span><br><span>@@ -1,4 +1,5 @@</span><br><span> ramstage-y += model_f3x_init.c</span><br><span> subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin</span><br><span>diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c</span><br><span>index d853a63..4b8168e 100644</span><br><span>--- a/src/cpu/intel/model_f3x/model_f3x_init.c</span><br><span>+++ b/src/cpu/intel/model_f3x/model_f3x_init.c</span><br><span>@@ -27,7 +27,7 @@</span><br><span> /* Turn on caching if we haven't already */</span><br><span> x86_enable_cache();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (!intel_ht_sibling()) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {</span><br><span> /* MTRRs are shared between threads */</span><br><span> x86_setup_mtrrs();</span><br><span> x86_mtrr_check();</span><br><span>@@ -40,7 +40,8 @@</span><br><span> setup_lapic();</span><br><span> </span><br><span> /* Start up my CPU siblings */</span><br><span style="color: hsl(0, 100%, 40%);">- intel_sibling_init(cpu);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_PARALLEL_MP))</span><br><span style="color: hsl(120, 100%, 40%);">+ intel_sibling_init(cpu);</span><br><span> };</span><br><span> </span><br><span> static struct device_operations cpu_dev_ops = {</span><br><span>diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc</span><br><span>index 2f11d7f..6fbc9ae 100644</span><br><span>--- a/src/cpu/intel/model_f4x/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_f4x/Makefile.inc</span><br><span>@@ -1,4 +1,5 @@</span><br><span> ramstage-y += model_f4x_init.c</span><br><span> subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin</span><br><span>diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c</span><br><span>index 9eb5115..c15cc97 100644</span><br><span>--- a/src/cpu/intel/model_f4x/model_f4x_init.c</span><br><span>+++ b/src/cpu/intel/model_f4x/model_f4x_init.c</span><br><span>@@ -27,7 +27,7 @@</span><br><span> /* Turn on caching if we haven't already */</span><br><span> x86_enable_cache();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (!intel_ht_sibling()) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {</span><br><span> /* MTRRs are shared between threads */</span><br><span> x86_setup_mtrrs();</span><br><span> x86_mtrr_check();</span><br><span>@@ -40,7 +40,8 @@</span><br><span> setup_lapic();</span><br><span> </span><br><span> /* Start up my CPU siblings */</span><br><span style="color: hsl(0, 100%, 40%);">- intel_sibling_init(cpu);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_PARALLEL_MP))</span><br><span style="color: hsl(120, 100%, 40%);">+ intel_sibling_init(cpu);</span><br><span> };</span><br><span> </span><br><span> static struct device_operations cpu_dev_ops = {</span><br><span>diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig</span><br><span>index dcf3fb5..05e2d49 100644</span><br><span>--- a/src/northbridge/intel/i945/Kconfig</span><br><span>+++ b/src/northbridge/intel/i945/Kconfig</span><br><span>@@ -29,6 +29,7 @@</span><br><span> select INTEL_EDID</span><br><span> select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span> select SMM_TSEG</span><br><span style="color: hsl(120, 100%, 40%);">+ select PARALLEL_MP</span><br><span> </span><br><span> config NORTHBRIDGE_INTEL_SUBTYPE_I945GC</span><br><span> def_bool n</span><br><span>diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c</span><br><span>index 94f7dac..7c1d540 100644</span><br><span>--- a/src/northbridge/intel/i945/northbridge.c</span><br><span>+++ b/src/northbridge/intel/i945/northbridge.c</span><br><span>@@ -136,26 +136,6 @@</span><br><span> pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Really doesn't belong here but will go away with parallel mp init,</span><br><span style="color: hsl(0, 100%, 40%);">- * so let it be here for a while...</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-int cpu_get_apic_id_map(int *apic_id_map)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int i;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Logical processors (threads) per core */</span><br><span style="color: hsl(0, 100%, 40%);">- const struct cpuid_result cpuid1 = cpuid(1);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Read number of cores. */</span><br><span style="color: hsl(0, 100%, 40%);">- const char cores = (cpuid1.ebx >> 16) & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TODO in parallel MP cpuid(1).ebx */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < cores; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- apic_id_map[i] = i;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return cores;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* TODO We could determine how many PCIe busses we need in</span><br><span> * the bar. For now that number is hardcoded to a max of 64.</span><br><span> * See e7525/northbridge.c for an example.</span><br><span>@@ -221,7 +201,7 @@</span><br><span> </span><br><span> static void cpu_bus_init(device_t dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- initialize_cpus(dev->link_list);</span><br><span style="color: hsl(120, 100%, 40%);">+ bsp_init_and_start_aps(dev->link_list);</span><br><span> }</span><br><span> </span><br><span> static struct device_operations cpu_bus_ops = {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25600">change 25600</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25600"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb </div>
<div style="display:none"> Gerrit-Change-Number: 25600 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>