<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25597">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/x4x: Use common code for SMM in TSEG<br><br>Untested<br><br>Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/x86/smm/smmrelocate.S<br>M src/northbridge/intel/x4x/Kconfig<br>M src/northbridge/intel/x4x/northbridge.c<br>M src/northbridge/intel/x4x/ram_calc.c<br>M src/northbridge/intel/x4x/x4x.h<br>M src/southbridge/intel/i82801jx/Makefile.inc<br>D src/southbridge/intel/i82801jx/smi.c<br>7 files changed, 63 insertions(+), 202 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/25597/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S</span><br><span>index ed556db..c2a0698 100644</span><br><span>--- a/src/cpu/x86/smm/smmrelocate.S</span><br><span>+++ b/src/cpu/x86/smm/smmrelocate.S</span><br><span>@@ -27,8 +27,6 @@</span><br><span> #include "../../../southbridge/intel/i82801dx/i82801dx.h"</span><br><span> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX)</span><br><span> #include "../../../southbridge/intel/i82801ix/i82801ix.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX)</span><br><span style="color: hsl(0, 100%, 40%);">-#include "../../../southbridge/intel/i82801jx/i82801jx.h"</span><br><span> </span><br><span> #else</span><br><span> #error "Southbridge needs SMM handler support."</span><br><span>diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig</span><br><span>index 9239637..087edad 100644</span><br><span>--- a/src/northbridge/intel/x4x/Kconfig</span><br><span>+++ b/src/northbridge/intel/x4x/Kconfig</span><br><span>@@ -28,6 +28,7 @@</span><br><span> select RELOCATABLE_RAMSTAGE</span><br><span> select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span> select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SMM_TSEG</span><br><span> </span><br><span> config CBFS_SIZE</span><br><span> hex</span><br><span>diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c</span><br><span>index 6ba45fe..52454cf 100644</span><br><span>--- a/src/northbridge/intel/x4x/northbridge.c</span><br><span>+++ b/src/northbridge/intel/x4x/northbridge.c</span><br><span>@@ -28,14 +28,15 @@</span><br><span> #include <northbridge/intel/x4x/iomap.h></span><br><span> #include <northbridge/intel/x4x/chip.h></span><br><span> #include <northbridge/intel/x4x/x4x.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/smm/gen1/smi.h></span><br><span> </span><br><span> static const int legacy_hole_base_k = 0xa0000 / 1024;</span><br><span> </span><br><span> static void mch_domain_read_resources(device_t dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u8 index, reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 index;</span><br><span> u64 tom, touud;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 tomk, tseg_sizek = 0, tolud;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tomk, tolud;</span><br><span> u32 pcie_config_base, pcie_config_size;</span><br><span> u32 uma_sizek = 0;</span><br><span> </span><br><span>@@ -79,20 +80,8 @@</span><br><span> uma_sizek += gsm_sizek;</span><br><span> </span><br><span> printk(BIOS_DEBUG, "TSEG decoded, subtracting ");</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(dev, D0F0_ESMRAMC);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 >>= 1;</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 &= 3;</span><br><span style="color: hsl(0, 100%, 40%);">- switch (reg8) {</span><br><span style="color: hsl(0, 100%, 40%);">- case 0:</span><br><span style="color: hsl(0, 100%, 40%);">- tseg_sizek = 1024;</span><br><span style="color: hsl(0, 100%, 40%);">- break; /* TSEG = 1M */</span><br><span style="color: hsl(0, 100%, 40%);">- case 1:</span><br><span style="color: hsl(0, 100%, 40%);">- tseg_sizek = 2048;</span><br><span style="color: hsl(0, 100%, 40%);">- break; /* TSEG = 2M */</span><br><span style="color: hsl(0, 100%, 40%);">- case 2:</span><br><span style="color: hsl(0, 100%, 40%);">- tseg_sizek = 8192;</span><br><span style="color: hsl(0, 100%, 40%);">- break; /* TSEG = 8M */</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 tseg_sizek = decode_tseg_size(</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config8(dev, D0F0_ESMRAMC));</span><br><span> uma_sizek += tseg_sizek;</span><br><span> tomk -= tseg_sizek;</span><br><span> </span><br><span>@@ -156,6 +145,43 @@</span><br><span> pci_write_config32(dev, PCI_COMMAND, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+u32 northbridge_get_tseg_size(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)),</span><br><span style="color: hsl(120, 100%, 40%);">+ D0F0_ESMRAMC);</span><br><span style="color: hsl(120, 100%, 40%);">+ return decode_tseg_size(esmramc);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u32 northbridge_get_tseg_base(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_TSEG);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void northbridge_write_smram(u8 smram)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_SMRAM, smram);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Really doesn't belong here but will go away with parallel mp init,</span><br><span style="color: hsl(120, 100%, 40%);">+ * so let it be here for a while...</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int cpu_get_apic_id_map(int *apic_id_map)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Logical processors (threads) per core */</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct cpuid_result cpuid1 = cpuid(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read number of cores. */</span><br><span style="color: hsl(120, 100%, 40%);">+ const char cores = (cpuid1.ebx >> 16) & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO in parallel MP cpuid(1).ebx */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < cores; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ apic_id_map[i] = i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return cores;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static struct device_operations pci_domain_ops = {</span><br><span> .read_resources = mch_domain_read_resources,</span><br><span> .set_resources = mch_domain_set_resources,</span><br><span>diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c</span><br><span>index 1009372..9783242 100644</span><br><span>--- a/src/northbridge/intel/x4x/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/x4x/ram_calc.c</span><br><span>@@ -52,6 +52,25 @@</span><br><span> return ggc2gtt[gsm] << 10;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/** Decodes used TSEG size to bytes. */</span><br><span style="color: hsl(120, 100%, 40%);">+u32 decode_tseg_size(const u32 esmramc)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(esmramc & 1))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch ((esmramc >> 1) & 3) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1 << 20;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 2 << 20;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 8 << 20;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 3:</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Bad TSEG setting.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> u8 decode_pciebar(u32 *const base, u32 *const len)</span><br><span> {</span><br><span> *base = 0;</span><br><span>diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h</span><br><span>index cbb1853..5c9682b 100644</span><br><span>--- a/src/northbridge/intel/x4x/x4x.h</span><br><span>+++ b/src/northbridge/intel/x4x/x4x.h</span><br><span>@@ -329,6 +329,7 @@</span><br><span> void x4x_late_init(int s3resume);</span><br><span> u32 decode_igd_memory_size(u32 gms);</span><br><span> u32 decode_igd_gtt_size(u32 gsm);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 decode_tseg_size(const u32 esmramc);</span><br><span> u8 decode_pciebar(u32 *const base, u32 *const len);</span><br><span> void sdram_initialize(int boot_path, const u8 *spd_map);</span><br><span> void raminit_ddr2(struct sysinfo *);</span><br><span>diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc</span><br><span>index d6a3a7d..e70932c 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/i82801jx/Makefile.inc</span><br><span>@@ -32,8 +32,6 @@</span><br><span> ramstage-y += ../i82801gx/reset.c</span><br><span> ramstage-y += ../i82801gx/watchdog.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S</span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span> </span><br><span> romstage-y += early_smbus.c</span><br><span>diff --git a/src/southbridge/intel/i82801jx/smi.c b/src/southbridge/intel/i82801jx/smi.c</span><br><span>deleted file mode 100644</span><br><span>index d55ad0e..0000000</span><br><span>--- a/src/southbridge/intel/i82801jx/smi.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,182 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- * 2012 secunet Security Networks AG</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(0, 100%, 40%);">- * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(0, 100%, 40%);">- * the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/cpu.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/common/pmutil.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "i82801jx.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* I945/GM45 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMRAM 0x9d</span><br><span style="color: hsl(0, 100%, 40%);">-#define D_OPEN (1 << 6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define D_CLS (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define D_LCK (1 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define G_SMRAME (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* While we read PMBASE dynamically in case it changed, let's</span><br><span style="color: hsl(0, 100%, 40%);">- * initialize it with a sane value</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 pmbase = DEFAULT_PMBASE;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-extern uint8_t smm_relocation_start, smm_relocation_end;</span><br><span style="color: hsl(0, 100%, 40%);">-static void *default_smm_area = NULL;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void smm_relocate(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 smi_en;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 pm1_en;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Initializing SMM handler...");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), D31F0_PMBASE) & 0xfffc;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en = inl(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_en & GBL_SMI_EN) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "SMI# handler already enabled?\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- default_smm_area = backup_default_smm_area();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* copy the SMM relocation code */</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy((void *)0x38000, &smm_relocation_start,</span><br><span style="color: hsl(0, 100%, 40%);">- &smm_relocation_end - &smm_relocation_start);</span><br><span style="color: hsl(0, 100%, 40%);">- wbinvd();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">- dump_smi_status(reset_smi_status());</span><br><span style="color: hsl(0, 100%, 40%);">- dump_pm1_status(reset_pm1_status());</span><br><span style="color: hsl(0, 100%, 40%);">- dump_gpe0_status(reset_gpe0_status());</span><br><span style="color: hsl(0, 100%, 40%);">- dump_alt_gp_smi_status(reset_alt_gp_smi_status());</span><br><span style="color: hsl(0, 100%, 40%);">- dump_tco_status(reset_tco_status());</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable SMI generation:</span><br><span style="color: hsl(0, 100%, 40%);">- * - on TCO events</span><br><span style="color: hsl(0, 100%, 40%);">- * - on APMC writes (io 0xb2)</span><br><span style="color: hsl(0, 100%, 40%);">- * - on writes to GBL_RLS (bios commands)</span><br><span style="color: hsl(0, 100%, 40%);">- * No SMIs:</span><br><span style="color: hsl(0, 100%, 40%);">- * - on microcontroller writes (io 0x62/0x66)</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en = 0; /* reset SMI enables */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= TCO_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= APMC_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-#if DEBUG_PERIODIC_SMIS</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set DEBUG_PERIODIC_SMIS in i82801jx.h to debug using</span><br><span style="color: hsl(0, 100%, 40%);">- * periodic SMIs.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= PERIODIC_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= BIOS_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* The following need to be on for SMIs to happen */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= EOS | GBL_SMI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- outl(smi_en, pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pm1_en = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- pm1_en |= PWRBTN_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- pm1_en |= GBL_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outw(pm1_en, pmbase + PM1_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /**</span><br><span style="color: hsl(0, 100%, 40%);">- * There are several methods of raising a controlled SMI# via</span><br><span style="color: hsl(0, 100%, 40%);">- * software, among them:</span><br><span style="color: hsl(0, 100%, 40%);">- * - Writes to io 0xb2 (APMC)</span><br><span style="color: hsl(0, 100%, 40%);">- * - Writes to the Local Apic ICR with Delivery mode SMI.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Using the local apic is a bit more tricky. According to</span><br><span style="color: hsl(0, 100%, 40%);">- * AMD Family 11 Processor BKDG no destination shorthand must be</span><br><span style="color: hsl(0, 100%, 40%);">- * used.</span><br><span style="color: hsl(0, 100%, 40%);">- * The whole SMM initialization is quite a bit hardware specific, so</span><br><span style="color: hsl(0, 100%, 40%);">- * I'm not too worried about the better of the methods at the moment</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* raise an SMI interrupt */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, " ... raise SMI#\n");</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x00, 0xb2);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int smm_handler_copied = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void smm_install(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* The first CPU running this gets to copy the SMM handler. But not all</span><br><span style="color: hsl(0, 100%, 40%);">- * of them.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- if (smm_handler_copied)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- smm_handler_copied = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* if we're resuming from S3, the SMM code is already in place,</span><br><span style="color: hsl(0, 100%, 40%);">- * so don't copy it again to keep the current SMM state */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!acpi_is_wakeup_s3()) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* enable the SMM memory window */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,</span><br><span style="color: hsl(0, 100%, 40%);">- D_OPEN | G_SMRAME | C_BASE_SEG);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* copy the real SMM handler */</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy((void *)0xa0000, _binary_smm_start,</span><br><span style="color: hsl(0, 100%, 40%);">- _binary_smm_end - _binary_smm_start);</span><br><span style="color: hsl(0, 100%, 40%);">- wbinvd();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* close the SMM memory window and enable normal SMM */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,</span><br><span style="color: hsl(0, 100%, 40%);">- G_SMRAME | C_BASE_SEG);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Put SMM code to 0xa0000 */</span><br><span style="color: hsl(0, 100%, 40%);">- smm_install();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Put relocation code to 0x38000 and relocate SMBASE */</span><br><span style="color: hsl(0, 100%, 40%);">- smm_relocate();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* We're done. Make sure SMIs can happen! */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_set_eos();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_init_completion(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- restore_default_smm_area(default_smm_area);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_lock(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* LOCK the SMM memory window and enable normal SMM.</span><br><span style="color: hsl(0, 100%, 40%);">- * After running this function, only a full reset can</span><br><span style="color: hsl(0, 100%, 40%);">- * make the SMM registers writable again.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Locking SMM.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,</span><br><span style="color: hsl(0, 100%, 40%);">- D_LCK | G_SMRAME | C_BASE_SEG);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25597">change 25597</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25597"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc </div>
<div style="display:none"> Gerrit-Change-Number: 25597 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>