<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25592">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/i945: Enable and allocate 8M for TSEG<br><br>TSEG can be used as a stage cache and SMM can be relocated here.<br><br>Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/i945/early_init.c<br>1 file changed, 5 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/25592/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c</span><br><span>index bf486a0..7de2c73 100644</span><br><span>--- a/src/northbridge/intel/i945/early_init.c</span><br><span>+++ b/src/northbridge/intel/i945/early_init.c</span><br><span>@@ -192,6 +192,11 @@</span><br><span>                gfxsize = 2;</span><br><span>         pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4));</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);</span><br><span style="color: hsl(120, 100%, 40%);">+   reg8 &= ~0x7;</span><br><span style="color: hsl(120, 100%, 40%);">+     reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+     pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>        /* Set C0000-FFFFF to access RAM on both reads and writes */</span><br><span>         pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);</span><br><span>  pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25592">change 25592</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25592"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd </div>
<div style="display:none"> Gerrit-Change-Number: 25592 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>