<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25595">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/i945: Use common SMM_TSEG code<br><br>Use the common SMM_TSEG code to relocate the smihandler to TSEG.<br><br>Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/model_106cx/Kconfig<br>M src/cpu/intel/model_106cx/Makefile.inc<br>M src/cpu/intel/model_6ex/Kconfig<br>M src/cpu/intel/model_6ex/Makefile.inc<br>M src/cpu/intel/model_f3x/Kconfig<br>M src/cpu/intel/model_f3x/Makefile.inc<br>M src/cpu/intel/model_f4x/Kconfig<br>M src/cpu/intel/model_f4x/Makefile.inc<br>M src/northbridge/intel/i945/Kconfig<br>M src/northbridge/intel/i945/i945.h<br>M src/northbridge/intel/i945/northbridge.c<br>M src/northbridge/intel/i945/ram_calc.c<br>M src/southbridge/intel/i82801gx/Makefile.inc<br>13 files changed, 51 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/25595/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig</span><br><span>index f365cf1..0cb47da 100644</span><br><span>--- a/src/cpu/intel/model_106cx/Kconfig</span><br><span>+++ b/src/cpu/intel/model_106cx/Kconfig</span><br><span>@@ -13,6 +13,7 @@</span><br><span>    select SUPPORT_CPU_UCODE_IN_CBFS</span><br><span>     select SERIALIZED_SMM_INITIALIZATION</span><br><span>         select CPU_INTEL_COMMON</span><br><span style="color: hsl(120, 100%, 40%);">+       select HAS_NO_SMRR</span><br><span> </span><br><span> if CPU_INTEL_MODEL_106CX</span><br><span> </span><br><span>diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc</span><br><span>index cd753db..0703099 100644</span><br><span>--- a/src/cpu/intel/model_106cx/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_106cx/Makefile.inc</span><br><span>@@ -1,5 +1,6 @@</span><br><span> ramstage-y += model_106cx_init.c</span><br><span> subdirs-y += ../../x86/name</span><br><span> subdirs-y += ../common</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin</span><br><span>diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig</span><br><span>index 10ebcc7..df1cbbb 100644</span><br><span>--- a/src/cpu/intel/model_6ex/Kconfig</span><br><span>+++ b/src/cpu/intel/model_6ex/Kconfig</span><br><span>@@ -11,3 +11,4 @@</span><br><span>   select TSC_SYNC_MFENCE</span><br><span>       select SUPPORT_CPU_UCODE_IN_CBFS</span><br><span>     select CPU_INTEL_COMMON</span><br><span style="color: hsl(120, 100%, 40%);">+       select HAS_NO_SMRR</span><br><span>diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc</span><br><span>index 4321f2a..13e08f0 100644</span><br><span>--- a/src/cpu/intel/model_6ex/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_6ex/Makefile.inc</span><br><span>@@ -1,5 +1,6 @@</span><br><span> ramstage-y += model_6ex_init.c</span><br><span> subdirs-y += ../../x86/name</span><br><span> subdirs-y += ../common</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin</span><br><span>diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig</span><br><span>index 7eaa820..0c6da97 100644</span><br><span>--- a/src/cpu/intel/model_f3x/Kconfig</span><br><span>+++ b/src/cpu/intel/model_f3x/Kconfig</span><br><span>@@ -6,3 +6,4 @@</span><br><span>     select ARCH_RAMSTAGE_X86_32</span><br><span>  select SMP</span><br><span>   select SUPPORT_CPU_UCODE_IN_CBFS</span><br><span style="color: hsl(120, 100%, 40%);">+      select HAS_NO_SMRR</span><br><span>diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc</span><br><span>index b73a25d..7367914 100644</span><br><span>--- a/src/cpu/intel/model_f3x/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_f3x/Makefile.inc</span><br><span>@@ -1,3 +1,4 @@</span><br><span> ramstage-y += model_f3x_init.c</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin</span><br><span>diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig</span><br><span>index 4ef60b5..c1e0dfd 100644</span><br><span>--- a/src/cpu/intel/model_f4x/Kconfig</span><br><span>+++ b/src/cpu/intel/model_f4x/Kconfig</span><br><span>@@ -6,3 +6,4 @@</span><br><span>      select ARCH_RAMSTAGE_X86_32</span><br><span>  select SMP</span><br><span>   select SUPPORT_CPU_UCODE_IN_CBFS</span><br><span style="color: hsl(120, 100%, 40%);">+      select HAS_NO_SMRR</span><br><span>diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc</span><br><span>index 9aeb107..2f11d7f 100644</span><br><span>--- a/src/cpu/intel/model_f4x/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_f4x/Makefile.inc</span><br><span>@@ -1,3 +1,4 @@</span><br><span> ramstage-y += model_f4x_init.c</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin</span><br><span>diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig</span><br><span>index 482f98a..dcf3fb5 100644</span><br><span>--- a/src/northbridge/intel/i945/Kconfig</span><br><span>+++ b/src/northbridge/intel/i945/Kconfig</span><br><span>@@ -28,6 +28,7 @@</span><br><span>        select RELOCATABLE_RAMSTAGE</span><br><span>  select INTEL_EDID</span><br><span>    select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+      select SMM_TSEG</span><br><span> </span><br><span> config NORTHBRIDGE_INTEL_SUBTYPE_I945GC</span><br><span>       def_bool n</span><br><span>diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h</span><br><span>index cc5f087..100ac9a 100644</span><br><span>--- a/src/northbridge/intel/i945/i945.h</span><br><span>+++ b/src/northbridge/intel/i945/i945.h</span><br><span>@@ -366,6 +366,7 @@</span><br><span> </span><br><span> u32 decode_igd_memory_size(u32 gms);</span><br><span> u32 decode_tseg_size(const u8 esmramc);</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t smm_region_start(void);</span><br><span> </span><br><span> #endif /* __ACPI__ */</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c</span><br><span>index 37f94b1..94f7dac 100644</span><br><span>--- a/src/northbridge/intel/i945/northbridge.c</span><br><span>+++ b/src/northbridge/intel/i945/northbridge.c</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #include <cbmem.h></span><br><span> #include <cpu/cpu.h></span><br><span> #include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/smm/gen1/smi.h></span><br><span> #include "i945.h"</span><br><span> </span><br><span> static int get_pcie_bar(u32 *base)</span><br><span>@@ -118,6 +119,43 @@</span><br><span>   assign_resources(dev->link_list);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+u32 northbridge_get_tseg_size(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)),</span><br><span style="color: hsl(120, 100%, 40%);">+                                        ESMRAMC);</span><br><span style="color: hsl(120, 100%, 40%);">+     return decode_tseg_size(esmramc);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u32 northbridge_get_tseg_base(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+        return (u32) smm_region_start();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void northbridge_write_smram(u8 smram)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+      pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Really doesn't belong here but will go away with parallel mp init,</span><br><span style="color: hsl(120, 100%, 40%);">+ * so let it be here for a while...</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int cpu_get_apic_id_map(int *apic_id_map)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+       unsigned int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+     /* Logical processors (threads) per core */</span><br><span style="color: hsl(120, 100%, 40%);">+   const struct cpuid_result cpuid1 = cpuid(1);</span><br><span style="color: hsl(120, 100%, 40%);">+  /* Read number of cores. */</span><br><span style="color: hsl(120, 100%, 40%);">+   const char cores = (cpuid1.ebx >> 16) & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+      /* TODO in parallel MP cpuid(1).ebx */</span><br><span style="color: hsl(120, 100%, 40%);">+        for (i = 0; i < cores; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+                apic_id_map[i] = i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return cores;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>   /* TODO We could determine how many PCIe busses we need in</span><br><span>    * the bar. For now that number is hardcoded to a max of 64.</span><br><span>          * See e7525/northbridge.c for an example.</span><br><span>diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c</span><br><span>index 5f3513a..aeace48 100644</span><br><span>--- a/src/northbridge/intel/i945/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/i945/ram_calc.c</span><br><span>@@ -43,7 +43,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static uintptr_t smm_region_start(void)</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t smm_region_start(void)</span><br><span> {</span><br><span>     uintptr_t tom;</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc</span><br><span>index bb68d93..70abbe2 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/i82801gx/Makefile.inc</span><br><span>@@ -33,8 +33,10 @@</span><br><span> ramstage-y += reset.c</span><br><span> ramstage-y += watchdog.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ifneq ($(CONFIG_SMM_TSEG),y)</span><br><span> ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c</span><br><span> ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span> </span><br><span> romstage-y += early_smbus.c early_lpc.c</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25595">change 25595</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25595"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9 </div>
<div style="display:none"> Gerrit-Change-Number: 25595 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>