<p>Naresh Solanki has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25547">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/{apl,glk}: Move flush_l1d_to_l2 function to common location<br><br>Move flush_l1d_l2 function to common location within the SoC.<br><br>BUG=None:<br>BRANCH=None<br>TEST= Build for glkrvp.<br><br>Change-Id: I4aaaaccc4f343bc4926111258a33e09e79c76141<br>Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com><br>---<br>M src/soc/intel/apollolake/car.c<br>M src/soc/intel/apollolake/include/soc/cpu.h<br>2 files changed, 11 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/25547/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c</span><br><span>index f46e0f8..920580d 100644</span><br><span>--- a/src/soc/intel/apollolake/car.c</span><br><span>+++ b/src/soc/intel/apollolake/car.c</span><br><span>@@ -20,19 +20,13 @@</span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <intelblocks/msr.h></span><br><span> #include <program_loading.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cpu.h></span><br><span> </span><br><span> /*</span><br><span>  * This file supports the necessary hoops one needs to jump through since</span><br><span>  * early FSP component and early stages are running from cache-as-ram.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void flush_l1d_to_l2(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-   msr_t msr = rdmsr(MSR_POWER_MISC);</span><br><span style="color: hsl(0, 100%, 40%);">-      msr.lo |= FLUSH_DL1_L2;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_POWER_MISC, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static inline int is_car_addr(uintptr_t addr)</span><br><span> {</span><br><span>   return ((addr >= CONFIG_DCACHE_RAM_BASE) &&</span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h</span><br><span>index ed4a7de..4a1a7a4 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/cpu.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/cpu.h</span><br><span>@@ -18,6 +18,9 @@</span><br><span> #ifndef _SOC_APOLLOLAKE_CPU_H_</span><br><span> #define _SOC_APOLLOLAKE_CPU_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Common Timer Copy (CTC) frequency - 19.2MHz. */</span><br><span> #define CTC_FREQ         19200000</span><br><span> </span><br><span>@@ -25,4 +28,11 @@</span><br><span> void apollolake_init_cpus(struct device *dev);</span><br><span> void mainboard_devtree_update(struct device *dev);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Flush L1D to L2 */</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void flush_l1d_to_l2(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+     msr_t msr = rdmsr(MSR_POWER_MISC);</span><br><span style="color: hsl(120, 100%, 40%);">+    msr.lo |= FLUSH_DL1_L2;</span><br><span style="color: hsl(120, 100%, 40%);">+       wrmsr(MSR_POWER_MISC, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> #endif /* _SOC_APOLLOLAKE_CPU_H_ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25547">change 25547</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25547"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4aaaaccc4f343bc4926111258a33e09e79c76141 </div>
<div style="display:none"> Gerrit-Change-Number: 25547 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Naresh Solanki <naresh.solanki@intel.com> </div>