<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25541">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Add GNB IOAPIC init<br><br>Use standard coreboot function to set virtual wire mode on<br>the GNB IOAPIC.<br><br>BUG=b:74104946<br>TEST=Check GNB IOAPIC debug output on serial.<br><br>Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0<br>Signed-off-by: Marc Jones <marc.jones@scarletltd.com><br>---<br>M src/soc/amd/stoneyridge/northbridge.c<br>1 file changed, 10 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/25541/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>index c640c1f..b725f9e 100644</span><br><span>--- a/src/soc/amd/stoneyridge/northbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/ioapic.h></span><br><span> #include <arch/acpi.h></span><br><span> #include <arch/acpigen.h></span><br><span> #include <cbmem.h></span><br><span>@@ -69,12 +70,20 @@</span><br><span> </span><br><span> static void read_resources(device_t dev)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+     struct resource *res;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>      /*</span><br><span>    * This MMCONF resource must be reserved in the PCI domain.</span><br><span>   * It is not honored by the coreboot resource allocator if it is in</span><br><span>   * the CPU_CLUSTER.</span><br><span>   */</span><br><span>  mmconf_resource(dev, MMIO_CONF_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+       /* NB IOAPIC2  resource */</span><br><span style="color: hsl(120, 100%, 40%);">+    res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ res->base = IO_APIC2_ADDR;</span><br><span style="color: hsl(120, 100%, 40%);">+ res->size = 0x00001000;</span><br><span style="color: hsl(120, 100%, 40%);">+    res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;</span><br><span> }</span><br><span> </span><br><span> static void set_resource(device_t dev, struct resource *resource, u32 nodeid)</span><br><span>@@ -165,6 +174,7 @@</span><br><span> </span><br><span> static void northbridge_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1);</span><br><span> }</span><br><span> </span><br><span> static unsigned long acpi_fill_hest(acpi_hest_t *hest)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25541">change 25541</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25541"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0 </div>
<div style="display:none"> Gerrit-Change-Number: 25541 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>