<p>Werner Zeh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25535">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">fsp_broadwell_de: Provide valid address and size for DCACHE range<br><br>On Broadwell-DE the FSP sets up DCACHE in the early call. The address<br>does not match the default FSP 1.0 address defined in<br>src/drivers/intel/fsp1_0/Kconfig which leads to errors when this range<br>is used in pre-ramstage stages.<br><br>This patch provides the matching DCACHE_RAM_BASE value among with a<br>suitable DCACHE_RAM_SIZE for the FSP based Broadwell-DE implementation.<br>The include order of Kconfig files makes sure that the Kconfig file in<br>the soc directory is sourced first and the defined values will override<br>the ones in src/drivers/intel/fsp1_0/Kconfig.<br><br>Change-Id: I2a55b576541a3d974ee2714b198095aa24fc46f5<br>Signed-off-by: Werner Zeh <werner.zeh@siemens.com><br>---<br>M src/soc/intel/fsp_broadwell_de/fsp/Kconfig<br>1 file changed, 16 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/25535/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig</span><br><span>index 2e1ebeb..4301be5 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig</span><br><span>@@ -21,6 +21,22 @@</span><br><span> The Broadwell-DE FSP is built with a preferred base address of</span><br><span> 0xffeb0000.</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config DCACHE_RAM_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xfe100000</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This address needs to match the setup performed inside FSP.</span><br><span style="color: hsl(120, 100%, 40%);">+ On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DCACHE_RAM_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x8000</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ The DCACHE is shared between FSP itself and the rest of the coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+ stages. A size of 0x8000 works fine while provides enough space for</span><br><span style="color: hsl(120, 100%, 40%);">+ features like VBOOT in verstage. Further increase to a power of two align</span><br><span style="color: hsl(120, 100%, 40%);">+ value leads to errors in FSP.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config FSP_MEMORY_DOWN</span><br><span> bool "Enable Memory Down"</span><br><span> default n</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25535">change 25535</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25535"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2a55b576541a3d974ee2714b198095aa24fc46f5 </div>
<div style="display:none"> Gerrit-Change-Number: 25535 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Werner Zeh <werner.zeh@siemens.com> </div>