<p>Justin TerAvest has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25538">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/octopus: Edge trigger cr50 interrupt<br><br>Interrupts from cr50 are edge-triggered, not level-triggered. This<br>change updates the GPIO configuration accordingly.<br><br>BUG=b:75306520<br>BRANCH=None<br>TEST=None<br><br>Change-Id: I0c5fb4495b404412a78965c2de7f00248d0c684b<br>Signed-off-by: Justin TerAvest <teravest@chromium.org><br>---<br>M src/mainboard/google/octopus/variants/baseboard/gpio.c<br>1 file changed, 2 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/25538/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c</span><br><span>index 3d5d925..8fe1205 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c</span><br><span>@@ -87,7 +87,7 @@</span><br><span>    PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */</span><br><span>      PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */</span><br><span>      PAD_CFG_GPI_APIC_IOS(GPIO_62, UP_20K, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* UART0-RTS_B */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+       PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */</span><br><span>        PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */</span><br><span>      PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */</span><br><span>    PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B */</span><br><span>@@ -264,7 +264,7 @@</span><br><span> static const struct pad_config early_gpio_table[] = {</span><br><span>     PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */</span><br><span>   /* GSPI0_INT */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,</span><br><span style="color: hsl(120, 100%, 40%);">+      PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,</span><br><span>               DISPUPD), /* H1_PCH_INT_ODL */</span><br><span>       /* GSPI0_CLK */</span><br><span>      PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25538">change 25538</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25538"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0c5fb4495b404412a78965c2de7f00248d0c684b </div>
<div style="display:none"> Gerrit-Change-Number: 25538 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Justin TerAvest <teravest@chromium.org> </div>