<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25526">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridege: Create AP jump structure<br><br>As part of moving AGESA calls from bootblock to romstage, create<br>infrastructure to pass a pointer to the AP cores, so they can jump directly<br>to romstage.<br><br>BUG=b:74236170<br>TEST=Build and boot grunt, actual test will be performed at a later patch.<br><br>Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>M src/soc/amd/stoneyridge/romstage.c<br>3 files changed, 62 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25526/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>index fafaf07..8f1ac5d 100644</span><br><span>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>@@ -30,19 +30,11 @@</span><br><span> #include <amdblocks/psp.h></span><br><span> #include <timestamp.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void bootblock_c_entry(uint64_t base_timestamp)</span><br><span style="color: hsl(120, 100%, 40%);">+static uintptr_t get_ap_ptr(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Call lib/bootblock.c main with BSP, shortcut for APs</span><br><span style="color: hsl(0, 100%, 40%);">- * todo: rearchitect AGESA entry points to remove need</span><br><span style="color: hsl(0, 100%, 40%);">- * to run amdinitreset, amdinitearly from bootblock.</span><br><span style="color: hsl(0, 100%, 40%);">- * Remove AP shortcut.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!boot_cpu())</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_soc_early_init(); /* APs will not return */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TSC cannot be relied upon. Override the TSC value passed in. */</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_main_with_timestamp(timestamp_get());</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Use the first IOAPIC scratch register */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, NB_IOAPIC_SCRATCH0);</span><br><span style="color: hsl(120, 100%, 40%);">+ return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA);</span><br><span> }</span><br><span> </span><br><span> /* Set the MMIO Configuration Base Address and Bus Range. */</span><br><span>@@ -65,10 +57,43 @@</span><br><span> set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_soc_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)</span><br><span> {</span><br><span> amd_initmmio();</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Call lib/bootblock.c main with BSP, shortcut for APs</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!boot_cpu()) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Before AGESA is moved to romstage, AP cores will</span><br><span style="color: hsl(120, 100%, 40%);">+ * reach this code before BSP can set the jump address,</span><br><span style="color: hsl(120, 100%, 40%);">+ * so ap_romstage_entry will be NULL.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ void (*ap_romstage_entry)(void) = (void (*)(void))get_ap_ptr();</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * TODO: Once AGESA calls are moved to romstage, remove</span><br><span style="color: hsl(120, 100%, 40%);">+ * this section of code.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ap_romstage_entry == NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_soc_early_init(); /* APs will not return */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "AP calling directly to romstage @%p\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ ap_romstage_entry);</span><br><span style="color: hsl(120, 100%, 40%);">+ ap_romstage_entry(); /* execution does not return */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TSC cannot be relied upon. Override the TSC value passed in. */</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_main_with_timestamp(timestamp_get());</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_soc_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * TODO: Once AGESA calls are moved to romstage, remove the</span><br><span style="color: hsl(120, 100%, 40%);">+ * if and bootblock_soc_init() as APs will never execute</span><br><span style="color: hsl(120, 100%, 40%);">+ * bootblock_soc_early_init().</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> if (!boot_cpu())</span><br><span> bootblock_soc_init(); /* APs will not return */</span><br><span> </span><br><span>@@ -117,6 +142,10 @@</span><br><span> u32 val = cpuid_eax(1);</span><br><span> printk(BIOS_DEBUG, "Family_Model: %08x\n", val);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * TODO: Once AGESA calls are moved to romstage, remove boot_cpu()</span><br><span style="color: hsl(120, 100%, 40%);">+ * from the if as APs will never execute bootblock_soc_init().</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> if (boot_cpu() && IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))</span><br><span> load_smu_fw1();</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>index d649ada..6e42b39 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>@@ -27,6 +27,13 @@</span><br><span> #define HT_INIT_CONTROL 0x6c</span><br><span> # define HTIC_BIOSR_DETECT ((1 << 5) | (1 << 9) | (1 << 10))</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* NB IOAPIC registers */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_INDEX 0xf8</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_DATA 0xfc</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_ADDRESS 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_SCRATCH0 0x3e</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_SCRATCH1 0x3f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* D18F1 - Address Map Registers */</span><br><span> </span><br><span> /* MMIO base and limit */</span><br><span>diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c</span><br><span>index 490fd9e..7911079 100644</span><br><span>--- a/src/soc/amd/stoneyridge/romstage.c</span><br><span>+++ b/src/soc/amd/stoneyridge/romstage.c</span><br><span>@@ -14,6 +14,7 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span> #include <arch/cpu.h></span><br><span> #include <arch/acpi.h></span><br><span> #include <cpu/x86/msr.h></span><br><span>@@ -31,6 +32,14 @@</span><br><span> #include <soc/northbridge.h></span><br><span> #include <soc/southbridge.h></span><br><span> #include <amdblocks/psp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <smp/node.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_ap_ptr(void *entry)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Use the first IOAPIC scratch register */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, NB_IOAPIC_SCRATCH0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, (u32)entry);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span> asmlinkage void car_stage_entry(void)</span><br><span> {</span><br><span>@@ -45,7 +54,10 @@</span><br><span> int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();</span><br><span> int i;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (boot_cpu()) {</span><br><span style="color: hsl(120, 100%, 40%);">+ console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ set_ap_ptr(car_stage_entry);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> if (!s3_resume) {</span><br><span> post_code(0x40);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25526">change 25526</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897 </div>
<div style="display:none"> Gerrit-Change-Number: 25526 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>